Patents by Inventor Maik Brett

Maik Brett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132186
    Abstract: A digitally modulated radar, DMR, transmitter module is disclosed comprising: a sequence generator, configured to generate a repeating digital sequence signal based on a relatively low-frequency clock signal; a mixer configured to combine the digital sequence signal with at least one phase-delayed copy of the digital sequence signal, to provide a combined signal; and a modulator configured to modulate a relatively high-frequency carrier signal, in dependence on the combined signal, to provide a modulated signal. Corresponding systems and methods are also disclosed.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 6, 2021
    Inventors: Gustavo Guarin Aristizabal, Ralf Reuter, Maik Brett
  • Publication number: 20210132215
    Abstract: Embodiments are disclosed that for synthetic aperture radar (SAR) systems and methods. Front-end circuitry transmits radar signals, receives return radar signals, and outputs digital radar data. FFT circuits process the digital radar data without zero-padding to generate FFT data corresponding to oversampled pixel range values. A processor further processes the FFT data to generate radar pixel data representing a radar image. Further, the FFT circuits can interpolate the FFT data based upon pixel ranges using a streamlined range computation process. This process pre-computes x-axis components for pixels in common rows and y-axis components for pixels in common columns within the FFT data. For one embodiment, a navigation processor is coupled to a SAR system within a vehicle, receives the radar pixel data, and causes one or more actions to occur based upon the radar pixel data, such as an advanced driver assistance system function or an autonomous driving function.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Ryan Haoyun Wu, Maik Brett, Michael Andreas Staudenmaier
  • Patent number: 10921434
    Abstract: A method of detecting an object is disclosed, comprising generating a transmission signal by generating a carrier signal and digitally modulating the carrier signal with a transmission modulation signal, and transmitting the transmission signal. A reflected signal is received, the reflected signal having been reflected from the object, and demodulated to extract a received modulation signal. The received modulation signal is correlated with the transmission modulation signal and a range of the object is determined from the correlation of the received modulation signal and the transmission modulation signal.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 16, 2021
    Assignee: NXP B.V.
    Inventors: Gustavo Guarin Aristizabal, Ralf Reuter, Maik Brett
  • Publication number: 20200408891
    Abstract: A device for a radar sensor is disclosed, the device comprising: transmission circuitry configured to generate transmission signals with a linear frequency chirp modulation in a predetermined frequency band for output to a radar antenna; reception circuitry configured to receive reflection signals corresponding to reflection of the transmitted radar signals from one or more physical objects; and control circuitry configured to select a frequency range within said predetermined frequency band and/or a timing pattern for said transmission signals; wherein said device is configured to: receive a further signal from a further radar sensor; determine, from said further signal, a frequency range and/or timing pattern in use by said further radar sensor for transmission of further transmission signals; and select a frequency range within said predetermined frequency band and/or a timing pattern for said transmission signals which does not conflict with the frequency range and/or timing pattern of said further transm
    Type: Application
    Filed: May 20, 2020
    Publication date: December 31, 2020
    Inventors: Maik Brett, Ryan Haoyun Wu, Arunesh Roy
  • Publication number: 20200379827
    Abstract: A method of acquiring data, a computer program product for implementing the method, a system for acquiring data, and a vehicle including the system. The method includes determining one or more data types and virtual channels required for one or more applications. The method also includes allocating a plurality of circular buffers in memory according to the determined data type(s) and virtual channel(s). One or more of the circular buffers are allocated to safety data lines. The remaining circular buffers are allocated to functional data lines. The method further includes storing at least one functional data line in a circular buffer allocated to functional data lines according to a data type and virtual channel of the functional data line. The method also includes storing at least one safety data line in a circular buffer allocated to safety data lines.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 3, 2020
    Inventors: Shreya Singh, Maik Brett, Arpita Agarwal, Shivali Jain, Anshul Goel, Naveen Kumar Jain
  • Publication number: 20200264295
    Abstract: A receiver unit is disclosed for use in a multiple-input-multiple output, MIMO, radar system having a plurality of transmitters each for transmitting one of a group of orthogonal digital-transmitter-signals on a carrier wave, the receiver unit configured and adapted to receive a raw-analog-signal on a carrier wave reflected from one or more target objects.
    Type: Application
    Filed: December 11, 2019
    Publication date: August 20, 2020
    Inventors: Gustavo Guarin Aristizabal, Ralf Reuter, Maik Brett
  • Publication number: 20200233059
    Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 23, 2020
    Inventors: MAIK BRETT, NAVEEN KUMAR JAIN, SHREYA SINGH
  • Patent number: 10649946
    Abstract: A system, method, and apparatus are provided for operating a device to receive a first signaling state sequence on a multi-wire interface within a first voltage range to cause the device to transition to a high-speed communication mode for receiving high-speed data on the multi-wire interface within a second, smaller voltage range before returning to a low-power communication mode when the device receives on the multi-wire interface a second sequence of two signaling states within the first voltage range to signal a turnaround command without requiring any additional signaling state within the first voltage range, where the turnaround command enables the device to transmit data from the device over the multi-wire interface by transmitting on the multi-wire interface the first sequence of signaling states within the first voltage range to cause the device to transition to a high-speed communication mode for transmitting data from the device over the multi-wire interface.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 12, 2020
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Naveen K. Jain, Shreya Singh
  • Patent number: 10558599
    Abstract: An apparatus for performing a method for loading a matrix into an accelerator includes an augmented direct memory access controller reading a matrix, in a data stream, from a first memory associated with a system processor and sending the matrix, in the data stream, to a second memory associated with the accelerator. The method further includes the augmented direct memory access controller extracting individual matrix elements from the data stream as the data stream is being sent to the second memory and analyzing the extracted individual matrix elements to determine if the matrix is any of a plurality of tested matrix class types as the data stream is being sent to the second memory.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 11, 2020
    Assignee: NXP USA, Inc.
    Inventors: Michael Andreas Staudenmaier, Leonardo Surico, Maik Brett
  • Patent number: 10409732
    Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: September 10, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael Andreas Staudenmaier, Leonardo Surico, Maik Brett
  • Publication number: 20190187245
    Abstract: A transceiver for a detection and ranging apparatus comprising: a transmitter chain comprising a first sequence generator configured to generate a first signal based on a digital sequence; an interference cancellation block comprising a second sequence generator configured to generate a second signal based on the same digital sequence used to generate the first signal, the second signal having a predetermined time delay relative to the first signal; and the receiver chain configured to receive a received signal for detection and ranging, the received signal having components comprising at least none, one, or more reflections of the transmission signal and a component comprising an interference signal, the receiver chain comprising a first analog signal mixer configured to provide an output signal by mixing the received signal and the second signal thereby cancelling the interference signal in the received signal.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Gustavo Guarin Aristizabal, Ralf Reuter, Maik Brett
  • Patent number: 10303736
    Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: May 28, 2019
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Navdeep Singh Gill, Rohit Tomar
  • Patent number: 10282387
    Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: May 7, 2019
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Navdeep Singh Gill, Rohit Tomar
  • Publication number: 20190079885
    Abstract: An apparatus for performing a method for loading a matrix into an accelerator includes an augmented direct memory access controller reading a matrix, in a data stream, from a first memory associated with a system processor and sending the matrix, in the data stream, to a second memory associated with the accelerator. The method further includes the augmented direct memory access controller extracting individual matrix elements from the data stream as the data stream is being sent to the second memory and analyzing the extracted individual matrix elements to determine if the matrix is any of a plurality of tested matrix class types as the data stream is being sent to the second memory.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 14, 2019
    Inventors: Michael Andreas Staudenmaier, Leonardo Surico, Maik Brett
  • Patent number: 10209345
    Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Deboleena Sakalley, Rohit Tomar
  • Publication number: 20180349290
    Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Michael Andreas Staudenmaier, Leonardo Surico, Maik Brett
  • Patent number: 9740663
    Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 22, 2017
    Assignee: NXP USA, Inc.
    Inventors: Rohit Tomar, Maik Brett, Tejbal Prasad, Gurinder Singh
  • Publication number: 20170132175
    Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described.
    Type: Application
    Filed: December 16, 2013
    Publication date: May 11, 2017
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Maik BRETT, Navdeep Singh GILL, Rohit TOMAR
  • Publication number: 20160314096
    Abstract: And FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data.
    Type: Application
    Filed: November 6, 2013
    Publication date: October 27, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Maik BRETT, Navdeep Singh GILL, Rohit TOMAR
  • Publication number: 20160266238
    Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.
    Type: Application
    Filed: October 21, 2013
    Publication date: September 15, 2016
    Inventors: Maik BRETT, Deboleena SAKALLEY, Rohit TOMAR