Abstract: A receiver unit is disclosed for use in a multiple-input-multiple output, MIMO, radar system having a plurality of transmitters each for transmitting one of a group of orthogonal digital-transmitter-signals on a carrier wave, the receiver unit configured and adapted to receive a raw-analog-signal on a carrier wave reflected from one or more target objects.

Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link.

Abstract: A system, method, and apparatus are provided for operating a device to receive a first signaling state sequence on a multi-wire interface within a first voltage range to cause the device to transition to a high-speed communication mode for receiving high-speed data on the multi-wire interface within a second, smaller voltage range before returning to a low-power communication mode when the device receives on the multi-wire interface a second sequence of two signaling states within the first voltage range to signal a turnaround command without requiring any additional signaling state within the first voltage range, where the turnaround command enables the device to transmit data from the device over the multi-wire interface by transmitting on the multi-wire interface the first sequence of signaling states within the first voltage range to cause the device to transition to a high-speed communication mode for transmitting data from the device over the multi-wire interface.

Abstract: An apparatus for performing a method for loading a matrix into an accelerator includes an augmented direct memory access controller reading a matrix, in a data stream, from a first memory associated with a system processor and sending the matrix, in the data stream, to a second memory associated with the accelerator. The method further includes the augmented direct memory access controller extracting individual matrix elements from the data stream as the data stream is being sent to the second memory and analyzing the extracted individual matrix elements to determine if the matrix is any of a plurality of tested matrix class types as the data stream is being sent to the second memory.

Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.

Abstract: A transceiver for a detection and ranging apparatus comprising: a transmitter chain comprising a first sequence generator configured to generate a first signal based on a digital sequence; an interference cancellation block comprising a second sequence generator configured to generate a second signal based on the same digital sequence used to generate the first signal, the second signal having a predetermined time delay relative to the first signal; and the receiver chain configured to receive a received signal for detection and ranging, the received signal having components comprising at least none, one, or more reflections of the transmission signal and a component comprising an interference signal, the receiver chain comprising a first analog signal mixer configured to provide an output signal by mixing the received signal and the second signal thereby cancelling the interference signal in the received signal.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.

Abstract: An apparatus for performing a method for loading a matrix into an accelerator includes an augmented direct memory access controller reading a matrix, in a data stream, from a first memory associated with a system processor and sending the matrix, in the data stream, to a second memory associated with the accelerator. The method further includes the augmented direct memory access controller extracting individual matrix elements from the data stream as the data stream is being sent to the second memory and analyzing the extracted individual matrix elements to determine if the matrix is any of a plurality of tested matrix class types as the data stream is being sent to the second memory.

Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.

Abstract: An electronic device includes a first memory subsystem, a second memory subsystem and a direct memory access controller. In response to a first type of request from a processor, the direct memory access controller requests data from the first memory subsystem and provides the data to the second memory subsystem. In response to a second type of request from a processor, the direct memory access controller requests an uncompressed matrix from the first memory subsystem, compresses the uncompressed matrix to generate a compressed matrix, and provides the compressed matrix to the second memory subsystem. In response to a third type of request from a processor, the direct memory access controller requests a compressed matrix from the second memory subsystem, un-compresses the compressed matric to generate an uncompressed matrix, and provides the un-compressed matrix to the first memory subsystem.

Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described.

Abstract: And FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data.

Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.

Abstract: A data processing device and a method for performing a round of an N point Fast Fourier Transform are described. The round comprises computing N output operands on the basis of N input operands by applying a set of N/P radix-P butterflies to the N input operands, wherein P is greater or equal two and the input operands are representable as N/(M*P)?2 input operand matrices, wherein M is greater or equal one, each input operand matrix is a square matrix with M*P lines and M*P columns, and each column of each input operand matrix contains the input operands for M of said butterflies.

Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.

Abstract: The invention relates to a method and a circuit arrangement for picture-in-picture insertion, in which a sequence of insertion pictures (Kj=K1,K2, . . . ) is read, with vertical decimation (VD?1), into a memory device (S) and subsequently read out, the sequence of insertion pictures (Kj) read out is inserted into a sequence of main pictures (Hi=H1, H2, . . . ) and the memory device (S) is continuously overwritten by the insertion pictures. In order to prevent the occurrence of a seam during the insertion of the insertion pictures into the main pictures in a cost-effective manner and with a relatively low outlay on apparatus, the memory device (S) is subdivided into memory segments (X,Y,Z) which are continuously cyclically overwritten by the insertion pictures, the memory device (S) has a storage capacity of less than two insertion pictures, and a decision is made as to whether the currently written insertion picture (Kj) or the immediately preceding insertion picture (Kj?1) is read out.

Abstract: In the case of picture insertions, such as picture-in-picture, for example, fluctuations in the line duration are manifested in position displacements relative to the desired position of the inserted pictures. In order to prevent position displacements in the horizontal direction, it is provided that the insertion position is corrected in a manner dependent on a determined line duration. The method according to the invention is suitable in particular for picture-in-picture insertions in television receivers.

Abstract: The invention relates to a method for changing the image size of video images, in which a decimation of video image signals (V) by an integral decimation factor (MHD, MVD) is carried out, and the decimated video image signals are subsequently read into an image memory for buffering. In order to achieve better possibilities of adjusting the image reduction with a relatively low outlay and high image quality, a fine decimation of the video image signals (V) is additionally carried out before buffering by a fine decimation factor (SHS, SVS) which can be adjusted to non-integral values, and a total decimation factor (MH, MV) relevant to the decimation of the video image signals (V) is formed from the integral decimation factor (MHD, MVD) and the fine decimation factor (SHS, SVS).