Abstract: A panel drive circuit having an input interface to which an image signal is input, a gamma correction circuit that corrects an image processing signal generated by an image processing circuit performing image processing on the image signal input to the input interface, such that a gamma correction signal thus generated has predetermined gamma characteristics, an unevenness correction circuit that corrects the gamma correction signal generated through the correction by the gamma correction circuit, based on correction data for reducing unevenness of a display panel, and an D/A convertor that has a variable output voltage range, and performs D/A conversion on an unevenness correction signal generated through the correction by the unevenness correction circuit and outputs the signal thus generated to the display panel, and the unevenness correction circuit changes the correction method according to the output voltage range of the D/A convertor.

Abstract: An unevenness correction data generation device suppressing the appearance of color unevenness when turning on R, G and B together includes a pattern generation unit causing red, green and blue images, in which display panel subpixels are turned on at the same gray level, to be displayed, a monochrome camera, a control unit generating first red, green and blue luminance correction data based on shooting data of the monochrome camera, a pattern generation unit causing the display panel to display a white image by causing red, green and blue images corrected with the respective luminance correction data to be displayed simultaneously, a color camera shooting the white image in color, and a control unit generating color correction data for correcting color unevenness based on shooting data of the color camera and generates unevenness correction data based on the red, green and blue luminance correction data and the color correction data.

Abstract: An input signal correction device for reducing power consumption is compatible with a variety of display panels, and includes an input circuit, extension/degeneration circuit, separation/recovery circuit and delay adjustment circuit operating at frequency f, demura circuit operating at frequency f/2, and adder circuit.

Abstract: An input signal correction device includes an input circuit, extension circuit, degenerate circuit, separation circuit, recovery circuit and delay adjustment circuit that operate at an operating frequency f, demura circuit that operates at an operating frequency f/2, and adder circuit. The extension circuit extends the period of R and B input signals by a factor of 2 and outputs preprocessing signals, the degenerate circuit degenerates a G input signal, the demura circuit corrects preprocessing signals from the extension and degenerate circuits and outputs correction signals, the separation circuit reduces the period of the R and B correction signals to ½ and outputs differential signals, recovery circuit reduces the period of G correction signal to ½ and outputs the same differential signal over two periods, the delay adjustment circuit delays the input and output signals, and the adder circuit adds the differential signals to the delay signals and outputs output signals.

Abstract: An unevenness correction system according to the present invention includes a panel drive circuit provided with a gamma correction circuit that performs gamma correction on an image signal input to an input interface, a gamma correction information acquisition circuit that acquires a gamma correction signal obtained through gamma correction as gamma correction information, an unevenness correction circuit that performs an unevenness correction on the gamma correction signal based on correction data, and an output interface that externally outputs the gamma correction information, and an unevenness correction apparatus provided with a pattern generator that outputs the image signal of a predetermined image to the input interface, and a control unit that generates correction data based on gamma correction information of each individual display panel input to and read by a gamma correction information reading unit from the output interface regarding the output image signal.

Abstract: An unevenness correction data generation device capable of preventing capturing of a black band caused by rewriting a display image when capturing an image of a display panel in order to generate unevenness correction data for the display panel. The device includes a pattern generation device configured to output an image signal and a synchronization signal to an organic EL panel; a camera configured to capture a display image of the organic EL panel to which the image signal was input; and an image quality adjustment device configured, based on the results of image capturing by the camera, to generate unevenness correction data for correcting unevenness of the organic EL panel. The camera captures the display image by opening a shutter from one vertical blanking period to another vertical blanking period of the display image, based on the synchronization signal from the pattern generation device.

Abstract: An unevenness correction system according to the present invention includes a panel drive circuit provided with a gamma correction circuit that performs gamma correction on an image signal input to an input interface, a gamma correction information acquisition circuit that acquires a gamma correction signal obtained through gamma correction as gamma correction information, an unevenness correction circuit that performs an unevenness correction on the gamma correction signal based on correction data, and an output interface that externally outputs the gamma correction information, and an unevenness correction apparatus provided with a pattern generator that outputs the image signal of a predetermined image to the input interface, and a control unit that generates correction data based on gamma correction information of each individual display panel input to and read by a gamma correction information reading unit from the output interface regarding the output image signal.

Abstract: An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Abstract: An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Abstract: An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Abstract: When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Abstract: An information device includes a main processing circuit for executing signal processing related to a main function in the information device, a main microcomputer for controlling the main processing circuit, a receiver circuit for interfacing with the outside of the information device, and an interface microcomputer for controlling the receiver circuit, the interface microcomputer being provided separately from the main microcomputer.

Abstract: A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.

Abstract: A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.

Abstract: A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.

Abstract: An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.