Patents by Inventor Makoto Inagaki
Makoto Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7830433Abstract: An amplification type solid state imaging device in use includes at least a light-receiving portion 10 formed by arranging on a semiconductor substrate 7 one-dimensionally or two-dimensionally a plurality of pixels that convert incident light to signal charge and output electric signals corresponding to the amount of the signal charge, a reader for reading out sequentially the electric signals from the respective pixels, a noise rejection circuit 11 for suppressing spurious signals for the electric signals read out by the reader, and a first light-shielding layer 1 positioned on the upper part of the light-receiving portion 10 so as to restrict entry of light into parts other than photoelectric conversion portions 10a of the pixels. Furthermore, a second light-shielding layer 2 for restricting entry of light into the noise rejection circuit 11 is provided on the upper part of the noise rejection circuit 11.Type: GrantFiled: July 27, 2005Date of Patent: November 9, 2010Assignee: Panasonic CorporationInventors: Takashi Fujioka, Masayuki Masuyama, Makoto Inagaki
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Publication number: 20100245642Abstract: A solid-state imaging device which can, in response to the problem of black-crush occurring in an image when strong light is enters the device, positively detect black-crush in a state in which a variance margin has been secured.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Applicant: PANASONIC CORPORATIONInventors: Hiroshi TOYA, Takashi FUJIOKA, Masayuki MASUYAMA, Makoto INAGAKI
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Publication number: 20100163712Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Panasonic CorporationInventors: Makoto INAGAKI, Yoshiyuki Matsunaga
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Publication number: 20100165162Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Panasonic CorporationInventors: Makoto INAGAKI, Yoshiyuki Matsunaga
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Publication number: 20100157123Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: PANASONIC CORPORATIONInventors: Makoto INAGAKI, Yoshiyuki Matsunaga
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Patent number: 7714920Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.Type: GrantFiled: February 15, 2008Date of Patent: May 11, 2010Assignee: Panasonic CorporationInventors: Makoto Inagaki, Yoshiyuki Matsunaga
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Patent number: 7696543Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.Type: GrantFiled: April 4, 2006Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Makoto Inagaki, Yoshiyuki Matsunaga
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Patent number: 7688373Abstract: In each photosensitive cell, a photodiode 101, a transfer gate 102, a floating diffusion layer section 103, an amplifier transistor 104, and a reset transistor 105 are formed in one active region surrounded by a device isolation region. The floating diffusion layer section 103 included in one photosensitive cell is connected not to the amplifier transistor 104 included in that cell but to the gate of the amplifier transistor 104 included in another photosensitive cell adjacent to the one photosensitive cell in the column direction. A polysilicon wire 111 connects the transfer gates 102 arranged in the same row, and a polysilicon wire 112 connects the reset transistors 105 arranged in the same row. For connection in the row direction, only polysilicon wires are used.Type: GrantFiled: September 29, 2006Date of Patent: March 30, 2010Assignee: Panasonic CorporationInventors: Makoto Inagaki, Yoshiyuki Matsunaga
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Patent number: 7671438Abstract: A solid-state imaging device includes first pixels and second pixels. Each of the first pixels and the second pixels includes a p-type diffusion layer formed in a semiconductor substrate and an n-type diffusion layer formed on the p-type diffusion layer. A first p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the first pixels. A second p-type implantation layer having a lower impurity concentration than the first p-type implantation layer or no p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the second pixels.Type: GrantFiled: April 15, 2008Date of Patent: March 2, 2010Assignee: Panasonic CorporationInventors: Makoto Inagaki, Masanori Kyougoku
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Publication number: 20090322924Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.Type: ApplicationFiled: August 6, 2009Publication date: December 31, 2009Applicant: PANASONIC CORPORATIONInventors: Makoto INAGAKI, Yoshiyuki Matsunaga
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Publication number: 20090295961Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.Type: ApplicationFiled: August 6, 2009Publication date: December 3, 2009Applicant: PANASONIC CORPORATIONInventors: Makoto INAGAKI, Yoshiyuki MATSUNAGA
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Publication number: 20090072125Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.Type: ApplicationFiled: October 27, 2008Publication date: March 19, 2009Applicant: Panasonic CorporationInventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
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Publication number: 20090026571Abstract: A solid-state imaging device includes first pixels and second pixels. Each of the first pixels and the second pixels includes a p-type diffusion layer formed in a semiconductor substrate and an n-type diffusion layer formed on the p-type diffusion layer. A first p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the first pixels. A second p-type implantation layer having a lower impurity concentration than the first p-type implantation layer or no p-type implantation layer is formed on a surface side of the semiconductor substrate on the n-type diffusion layer of the second pixels.Type: ApplicationFiled: April 15, 2008Publication date: January 29, 2009Inventors: Makoto Inagaki, Masanori Kyougoku
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Publication number: 20090021625Abstract: According to the present invention, as a structure of a pixel section (10), in each of columns from a first to a m-th column, a plurality of pixel signals outputted from a plurality of pixels arranged in a column direction are transmitted, respectively, to a plurality of output signal lines (15l to 15n) different from each other. Then, a read control and are set control are simultaneously executed on the plurality of pixels.Type: ApplicationFiled: October 24, 2006Publication date: January 22, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takeshi Sowa, Kunihiko Hara, Makoto Inagaki, Yoshiyuki Matsunaga
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Publication number: 20090021620Abstract: A plurality of pixels, each including a second conductivity-type photodiode portion 1 formed in a first conductivity-type well region and an amplifier transistor 6 for amplifying and outputting charge accumulated in the photodiode portion, are arrayed two-dimensionally. Furthermore, an intra-pixel contact 2 for providing the well region with a reference voltage is provided in the photodiode portion. With this configuration, it is possible to achieve a rational intra-pixel GND contact arrangement with which the afterimage characteristics are improved and the optical characteristics are not affected adversely.Type: ApplicationFiled: August 2, 2005Publication date: January 22, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Makoto Inagaki, Kazuaki Igaki, Motohiro Kojima
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Patent number: 7459335Abstract: A solid-state imaging apparatus includes a plurality of photosensitive cells, and a driving unit provided for driving the plurality of photosensitive cells. Each photosensitive cell includes a photodiode formed to be exposed on a surface of a semiconductor substrate for the purpose of accumulating signal charge obtained by subjecting incident light to photoelectric conversion, a transfer transistor for transferring signal charge accumulated by the photodiode, a floating diffusion layer for temporarily accumulating signal charge transferred by the transfer transistor, and an amplifier transistor for amplifying signal charge temporarily accumulated in the floating diffusion layer. A source/drain diffusion layer provided in the amplifier transistor is covered with a salicide layer, and the floating diffusion layer is formed to be exposed on a surface of the semiconductor substrate.Type: GrantFiled: March 22, 2007Date of Patent: December 2, 2008Assignee: Panasonic CorporationInventors: Mikiya Uchida, Yoshiyuki Matsunaga, Makoto Inagaki
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Publication number: 20080231733Abstract: An amplification type solid state imaging device in use includes at least a light-receiving portion 10 formed by arranging on a semiconductor substrate 7 one-dimensionally or two-dimensionally a plurality of pixels that convert incident light to signal charge and output electric signals corresponding to the amount of the signal charge, a reader for reading out sequentially the electric signals from the respective pixels, a noise rejection circuit 11 for suppressing spurious signals for the electric signals read out by the reader, and a first light-shielding layer 1 positioned on the upper part of the light-receiving portion 10 so as to restrict entry of light into parts other than photoelectric conversion portions 10a of the pixels. Furthermore, a second light-shielding layer 2 for restricting entry of light into the noise rejection circuit 11 is provided on the upper part of the noise rejection circuit 11.Type: ApplicationFiled: July 27, 2005Publication date: September 25, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takashi Fujioka, Masayuki Masuyama, Makoto Inagaki
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Publication number: 20080143861Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.Type: ApplicationFiled: February 15, 2008Publication date: June 19, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
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Publication number: 20080087925Abstract: During an exposure time period (long accumulation time period) of a low shutter speed shooting mode, a second reference voltage Vss2, which is different from a first reference voltage Vss1 (a ground voltage) corresponding to a reference voltage of a peripheral circuit, is applied to a well (5) where a photoelectric converter section (2) and a drain region (4) are formed, whereby generation of dark electrons at a portion of a surface of the well (5) below a gate electrode (6) is suppressed. A polarity of the second reference voltage Vss2 is positive in the case where a conductivity type of the well (5) is a P-type, and is negative in the case of an N-type.Type: ApplicationFiled: July 21, 2005Publication date: April 17, 2008Inventors: Makoto Inagaki, Yoshiyuki Matsunaga
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Patent number: 7352399Abstract: Photosensitive cells each includes a photodiode (1), a transfer gate (2), a floating diffusion layer portion (3), an amplifying transistor (4), and a reset transistor (5). Drains of the amplifying transistors (4) of the photosensitive cells are connected to a power supply line (10), and a pulsed power supply voltage (VddC) is applied to the power supply line (10). Here, a low-level potential (VddC_L) of the power supply voltage has a predetermined potential higher than zero potential. Specifically, by making the low-level potential (VddC_L) higher than channel potentials obtained when a low level is applied to the reset transistors (5), or channel potentials obtained when a low level is applied to the transfer gates (2), or channel potentials of the photodiodes (1), a reproduced image with low noise is read.Type: GrantFiled: February 26, 2004Date of Patent: April 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Inagaki, Yoshiyuki Matsunaga