Patents by Inventor Makoto Iwai

Makoto Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Light-Emitting Element and Laminate Containing Same
    Publication number: 20140158978
    Abstract: A semiconductor light emitting device includes a film of a nitride of a group 13 element grown on a seed crystal substrate by flux method from a melt including a flux and a group 13 element under nitrogen containing atmosphere, an n-type semiconductor layer provided on the film of the nitride, a light emitting region provided on the n-type semiconductor layer, and a p-type semiconductor layer provided on the light emitting region. The film includes an inclusion distributed layer in a region distant by 50 ?m or less from an interface of the film on the side of the seed crystal substrate and including inclusions derived from components of the melt, and an inclusion depleted layer with the inclusion depleted formed on the inclusion distributed layer.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 12, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Makoto Iwai, Takayuki Hirao, Takashi Yoshino
  • Nonvolatile semiconductor memory
    Patent number: 8750039
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • Method for Peeling Group 13 Element Nitride Film
    Publication number: 20140147953
    Abstract: A film 3 of a nitride of a group 13 element is grown on a seed crystal substrate 11 by flux process from a melt containing a flux and the group 13 element under nitrogen containing atmosphere. The film 3 of the nitride of the group 13 element includes an inclusion distributed layer 3a in a region distant from an interface 11a of the film 3 of the nitride of the group 13 element on the side of the seed crystal substrate 11 and containing inclusions derived from components of the melt, and an inclusion depleted layer 3b, with the inclusion depleted. provided on the layer 3a. Laser light A is irradiated from the side of the back face 1b of the seed crystal substrate 11 to peel the single crystal 3 of the nitride of the group 13 element from the seed crystal substrate 11 by laser lift-off method.
    Type: Application
    Filed: January 29, 2014
    Publication date: May 29, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Makoto Iwai, Takayuki Hirao, Takashi Yoshino
  • Composite Substrates, A Method of Producing the Same, A Method of Producing Functional Layers Made of Nitrides of Group 13 Elements, and Functional Devices
    Publication number: 20140103362
    Abstract: A composite substrate 10 includes a sapphire body 1A, a seed crystal film 4 composed of gallium nitride crystal and provided on a surface of the sapphire body, and a gallium nitride crystal layer 7 grown on the seed crystal film 4 and having a thickness of 200 ?m or smaller. Voids 5 are provided along an interface between the sapphire body 1A and the seed crystal film 4 in a void ratio of 4.5 to 12.5 percent.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 17, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Makoto Iwai
  • Composite Substrates, Light Emitting Devices and a Method of Producing Composite Substrates
    Publication number: 20140054605
    Abstract: A plurality of protrusions 3 are provided on a c-face 2a of a sapphire body 2. An underlying layer 5 made of gallium nitride is then grown by vapor phase epitaxy process on the c-face 2a. A gallium nitride crystal layer 6 is then provided by flux method on the underlying layer 5. Each of the protrusions 3 has a shape of a hexagonal prism or a six-sided pyramid. Differences of growth rates of the gallium nitride crystal around the protrusions 3 are utilized to relax a stress between the sapphire body and gallium nitride crystal and to reduce cracks or fractures due to the stress.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 27, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Makoto Iwai, Yoshitaka Kuraoka
  • Melt composition for gallium nitride single crystal growth and method for growing gallium nitride single crystal
    Patent number: 8657955
    Abstract: It is provided a melt composition for growing a gallium nitride single crystal by flux method. The melt composition contains gallium, sodium and barium, and a content of barium is 0.05 to 0.3 mol % with respect to 100 mol % of sodium.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: February 25, 2014
    Assignees: NGK Insulators, Ltd, Osaka University, Toyoda Gosei Co., Ltd.
    Inventors: Makoto Iwai, Takanao Shimodaira, Yoshihiko Yamamura, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Shiro Yamasaki
  • Bis [tri (hydroxypolyalkyleneoxy) silylalkyl] polysulfide, method of manufacturing bis [tri (hydroxypolyalkyleneoxy) silylalkyl] polysulfide, tire rubber additive, and tire rubber composition
    Patent number: 8642690
    Abstract: A bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide, i.e., a polysulfide that contains bonded hydroxypolyalkyleneoxy groups instead of alkoxy groups in the bis(trialkoxysilylalkyl) polysulfide; a method of manufacturing of the aforementioned polysulfide by heating a bis(trialkoxysilylalkyl) polysulfide and a polyalkyleneglycol; a tire rubber additive to a tire rubber composition that comprises a bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide alone or a mixture of bis[tri(hydroxypolyalkyleneoxy)silylalkyl] polysulfide and a polyalkyleneglycol; and a tire rubber composition that contains the aforementioned additive.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: February 4, 2014
    Assignees: Dow Corning Corporation, Dow Corning Toray Company, Ltd.
    Inventors: Takeaki Saiki, Makoto Iwai, Haruhiko Furukawa, Anil Kumar Tomar
  • Process for Producing Group 13 Metal Nitride, and Seed Crystal Substrate for Use in Same
    Publication number: 20140026809
    Abstract: A seed crystal substrate 10 includes a supporting body 1, and a seed crystal film 3A formed on the supporting body 1 and composed of a single crystal of a nitride of a Group 13 metal element. The seed crystal film 3A includes main body parts 3a and thin parts 3b having a thickness smaller than that of the main body parts 3a. The main body parts 3a and thin part 3b are exposed to a surface of the seed crystal substrate 10. A nitride 15 of a Group 13 metal element is grown on the seed crystal film 3A by flux method.
    Type: Application
    Filed: September 17, 2013
    Publication date: January 30, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Makoto Iwai, Takanao Shimodaira, Shuhei Higashihara, Takayuki Hirao, Masahiro Sakai, Katsuhiro Imai
  • Method for Producing Gallium Nitride Layer and Seed Crystal Substrate Used in Same
    Publication number: 20140014028
    Abstract: A gallium nitride layer is produced using a seed crystal substrate by flux method. The seed crystal substrate 8A includes a supporting body 1, a plurality of seed crystal layers 4A each comprising gallium nitride single crystal and separated from one another, a low temperature buffer layer 2 provided between the seed crystal layers 4A and the supporting body and made of a nitride of a group III metal element, and an exposed layer 3 exposed to spaces between the adjacent seed crystal layers 4A and made of aluminum nitride single crystal or aluminum gallium nitride single crystal. The gallium nitride layer is grown on the seed crystal layers by flux method.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 16, 2014
    Applicant: NGK INSULATORS, LTD.
    Inventors: Katsuhiro Imai, Makoto Iwai, Takanao Shimodaira, Masahiro Sakai, Shuhei Higashihara, Takayuki Hirao
  • NONVOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20140010010
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Application
    Filed: September 11, 2013
    Publication date: January 9, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20130314996
    Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a cell well in a row direction and a column direction in a matrix; word lines which select the memory cell in the row direction; bit lines which select the memory cell in the column direction; a sense amplifier which determines a value stored in the memory cell based on a potential of the bit line; a peripheral transistor in the memory cell array which is arranged in the periphery of the memory cell array; and an enhancement type transistor which drives a gate of the peripheral transistor.
    Type: Application
    Filed: March 19, 2013
    Publication date: November 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Makoto IWAI
  • Method for growing single crystal of group III metal nitride and reaction vessel for use in same
    Patent number: 8568532
    Abstract: Materials of a nitride single crystal of a metal belonging to III group and a flux are contained in a crucible, which is contained in a reaction container, the reaction container is contained in an outer container, the outer container is contained in a pressure container, and nitrogen-containing atmosphere is supplied into the outer container and melt is generated in the crucible to grow a nitride single crystal of a metal belonging to III group. The reaction container includes a main body containing the crucible and a lid. The main body includes a side wall having a fitting face and a groove opening at the fitting face and a bottom wall. The lid has an upper plate part including a contact face for the fitting face of the main body and a flange part extending from the upper plate part and surrounding an outer side of said side wall.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: October 29, 2013
    Assignees: NGK Insulators, Ltd.
    Inventors: Makoto Iwai, Shuhei Higashihara, Yusuke Mori, Yasuo Kitaoka, Naoya Miyoshi
  • Nonvolatile semiconductor memory
    Patent number: 8559222
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Iwai, Hirsohi Nakamura
  • NONVOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20130250681
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Application
    Filed: May 22, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • N-type group III nitride-based compound semiconductor and production method therefor
    Patent number: 8507364
    Abstract: An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal. The mole percentage of germanium to gallium in the melt is 0.05 mol % to 0.5 mol %, and the mole percentage of carbon to sodium is 0.1 mol % to 3.0 mol %.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: August 13, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Seiji Nagai, Shiro Yamazaki, Yasuhide Yakushi, Takayuki Sato, Makoto Iwai, Katsuhiro Imai, Yusuke Mori, Yasuo Kitaoka
  • Method for manufacturing nitride single crystal
    Patent number: 8506705
    Abstract: A nitride single crystal is produced on a seed crystal substrate 5 in a melt containing a flux and a raw material of the single crystal in a growing vessel 1. The melt 2 in the growing vessel 1 has temperature gradient in a horizontal direction. In growing a nitride single crystal by flux method, adhesion of inferior crystals onto the single crystal is prevented and the film thickness of the single crystal is made constant.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: August 13, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Mikiya Ichimura, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Yasuo Kitaoka
  • Method for producing group III nitride semiconductor
    Patent number: 8501141
    Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 6, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd., Osaka University
    Inventors: Takayuki Sato, Seiji Nagai, Makoto Iwai, Shuhei Higashihara, Yusuke Mori, Yasuo Kitaoka
  • Process for producing single crystal
    Patent number: 8486190
    Abstract: A raw material mixture containing an easily oxidizable material is weighed. The raw material mixture is melted and then solidified within a reaction vessel 1 set in a non-oxidizing atmosphere to thereby produce a solidified matter 19. The reaction vessel 1 and the solidified matter 19 are heated in a non-oxidizing atmosphere within a crystal growth apparatus to melt the solidified matter to thereby produce a solution. A single crystal is grown from the solution.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: July 16, 2013
    Assignees: NGK Insulators, Ltd., Osaka University
    Inventors: Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Nonvolatile semiconductor memory
    Patent number: 8477534
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20130051147
    Abstract: A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potential lower than the first potential to the second select gate transistors, gives a third potential to the memory cells which are insufficient in the writing, gives a fourth potential higher than the third potential to the memory cells which are just before completion of the writing, and gives a fifth potential higher than the fourth potential to the memory cells which are completed in the writing. The first potential is capable of turning on the second select gate transistors. The second potential is capable of turning off the second select gate transistors.
    Type: Application
    Filed: April 18, 2012
    Publication date: February 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Makoto IWAI