Patents by Inventor Makoto Kaneyasu
Makoto Kaneyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061292Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: October 17, 2023Publication date: February 22, 2024Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 11796866Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: September 21, 2022Date of Patent: October 24, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Publication number: 20230012554Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 11493808Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: May 21, 2021Date of Patent: November 8, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Patent number: 11187944Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: October 2, 2020Date of Patent: November 30, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Publication number: 20210278715Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: May 21, 2021Publication date: September 9, 2021Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 11092856Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: October 2, 2020Date of Patent: August 17, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Publication number: 20210026173Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: October 2, 2020Publication date: January 28, 2021Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Publication number: 20210026174Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: October 2, 2020Publication date: January 28, 2021Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 10824028Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: November 27, 2019Date of Patent: November 3, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Patent number: 10651203Abstract: To provide an input device and an input/output device with high detection sensitivity. The input device includes a first transistor, a second transistor, a capacitor, a node, a first wiring, a second wiring, a third wiring, and a fourth wiring. The first transistor includes a first gate and a second gate. The first and second gates of the first transistor overlap with each other with a semiconductor film therebetween. The second gate of the first transistor is electrically connected to the node. The first wiring is electrically connected to the second wiring through the first transistor. The third wiring is electrically connected to the node through the second transistor. A first terminal of the capacitor is electrically connected to the node, and a second terminal of the capacitor is electrically connected to the fourth wiring.Type: GrantFiled: June 5, 2015Date of Patent: May 12, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Makoto Kaneyasu
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Publication number: 20200124889Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: ApplicationFiled: November 27, 2019Publication date: April 23, 2020Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
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Patent number: 10539839Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.Type: GrantFiled: February 3, 2016Date of Patent: January 21, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroyuki Miyake, Makoto Kaneyasu
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Patent number: 10437123Abstract: A novel liquid crystal display device is provided. Two pixels each include a transistor that includes a back gate. The transistor is connected to the common gate line and data line. A threshold voltage is controlled by a control signal supplied to a back gate so that while data is written to one pixel, the transistor of the other pixel is not turned on. The aperture ratio is improved by reducing the number of wirings connected to the pixel and increasing the frequency of the control signal supplied to the back gate.Type: GrantFiled: June 23, 2016Date of Patent: October 8, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Daisuke Kubota, Makoto Kaneyasu
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Patent number: 10217772Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.Type: GrantFiled: April 23, 2018Date of Patent: February 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
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Patent number: 10139663Abstract: An input/output device is provided. The input/output device includes a first pixel electrode, a second pixel electrode, a first common electrode, a second common electrode, a liquid crystal, a first insulating film, a second insulating film, and a transistor. The first common electrode can serve as one electrode of a sensor element. The second common electrode can serve as the other electrode of the sensor element. The transistor includes a first gate, a second gate, and a semiconductor layer. The pixel electrode, the common electrodes, and the second gate are positioned on different planes. The second gate contains one or more kinds of metal elements included in the semiconductor layer. The second gate, the pixel electrode, and the common electrodes preferably contain one or more kinds of metal elements included in the semiconductor layer.Type: GrantFiled: May 12, 2016Date of Patent: November 27, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Koji Kusunoki, Kouhei Toyotaka, Kazunori Watanabe, Makoto Kaneyasu
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Publication number: 20180308866Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.Type: ApplicationFiled: April 23, 2018Publication date: October 25, 2018Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
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Publication number: 20180180960Abstract: A novel liquid crystal display device is provided. Two pixels each include a transistor that includes a back gate. The transistor is connected to the common gate line and data line. A threshold voltage is controlled by a control signal supplied to a back gate so that while data is written to one pixel, the transistor of the other pixel is not turned on. The aperture ratio is improved by reducing the number of wirings connected to the pixel and increasing the frequency of the control signal supplied to the back gate.Type: ApplicationFiled: June 23, 2016Publication date: June 28, 2018Inventors: Daisuke KUBOTA, Makoto KANEYASU
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Patent number: 9985052Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.Type: GrantFiled: October 24, 2017Date of Patent: May 29, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Makoto Kaneyasu
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Patent number: 9954011Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.Type: GrantFiled: December 16, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu