Patents by Inventor Makoto Kaneyasu

Makoto Kaneyasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180047758
    Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Kaneyasu
  • Publication number: 20180011355
    Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.
    Type: Application
    Filed: February 3, 2016
    Publication date: January 11, 2018
    Inventors: Hiroyuki MIYAKE, Makoto KANEYASU
  • Patent number: 9806098
    Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Kaneyasu
  • Publication number: 20170213851
    Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
    Type: Application
    Filed: December 16, 2016
    Publication date: July 27, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki SHISHIDO, Hiroyuki MIYAKE, Kouhei TOYOTAKA, Makoto KANEYASU
  • Patent number: 9600107
    Abstract: To provide a touch panel in which a decrease in display quality is suppressed. The touch panel includes a touch sensor and a display element. The touch sensor includes a transistor and a sensor element. The transistor is electrically connected to the sensor element. The sensor element includes a pair of electrodes and a dielectric layer. The dielectric layer is positioned between the pair of electrodes. One of the pair of electrodes is an island-shaped electrode. The display element can display an image toward the touch sensor side. The island-shaped electrode does not overlap with a display region of the display element.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Kaneyasu, Kazunori Watanabe, Hiroyuki Miyake
  • Patent number: 9525017
    Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: December 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
  • Publication number: 20160349557
    Abstract: An input/output device is provided. The input/output device includes a first pixel electrode, a second pixel electrode, a first common electrode, a second common electrode, a liquid crystal, a first insulating film, a second insulating film, and a transistor. The first common electrode can serve as one electrode of a sensor element. The second common electrode can serve as the other electrode of the sensor element. The transistor includes a first gate, a second gate, and a semiconductor layer. The pixel electrode, the common electrodes, and the second gate are positioned on different planes. The second gate contains one or more kinds of metal elements included in the semiconductor layer. The second gate, the pixel electrode, and the common electrodes preferably contain one or more kinds of metal elements included in the semiconductor layer.
    Type: Application
    Filed: May 12, 2016
    Publication date: December 1, 2016
    Inventors: Hideaki SHISHIDO, Koji KUSUNOKI, Kouhei TOYOTAKA, Kazunori WATANABE, Makoto KANEYASU
  • Patent number: 9451246
    Abstract: A display device includes a display panel including a plurality of pixels, a shutter panel including a driver circuit, a liquid crystal, and light-transmitting electrodes provided in a striped manner, and a positional data detector configured to detect a positional data of a viewer. The shutter panel is provided over a display surface side of the display panel, a width of one of the light-transmitting electrodes in the shutter panel is smaller than that of one of the plurality of pixels, and the driver circuit in the shutter panel is configured to selectively output signals for forming a parallax barrier to the light-transmitting electrodes. The parallax barrier is capable of changing its shape in accordance with the detected positional data.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: September 20, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun Koyama, Hiroyuki Miyake, Hideaki Shishido, Seiko Inoue, Kouhei Toyotaka, Koji Kusunoki, Hikaru Harada, Makoto Kaneyasu
  • Publication number: 20160079333
    Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 17, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Hiroyuki Miyake, Kouhei Toyotaka, Makoto Kaneyasu
  • Publication number: 20150364496
    Abstract: To provide an input device and an input/output device with high detection sensitivity. The input device includes a first transistor, a second transistor, a capacitor, a node, a first wiring, a second wiring, a third wiring, and a fourth wiring. The first transistor includes a first gate and a second gate. The first and second gates of the first transistor overlap with each other with a semiconductor film therebetween. The second gate of the first transistor is electrically connected to the node. The first wiring is electrically connected to the second wiring through the first transistor. The third wiring is electrically connected to the node through the second transistor. A first terminal of the capacitor is electrically connected to the node, and a second terminal of the capacitor is electrically connected to the fourth wiring.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 17, 2015
    Inventor: Makoto KANEYASU
  • Publication number: 20150261333
    Abstract: To provide a touch panel in which a decrease in display quality is suppressed. The touch panel includes a touch sensor and a display element. The touch sensor includes a transistor and a sensor element. The transistor is electrically connected to the sensor element. The sensor element includes a pair of electrodes and a dielectric layer. The dielectric layer is positioned between the pair of electrodes. One of the pair of electrodes is an island-shaped electrode. The display element can display an image toward the touch sensor side. The island-shaped electrode does not overlap with a display region of the display element.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 17, 2015
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto KANEYASU, Kazunori WATANABE, Hiroyuki MIYAKE
  • Patent number: 9111483
    Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka, Kazunori Watanabe, Toru Tanabe, Makoto Kaneyasu, Masashi Fujita
  • Publication number: 20150162359
    Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventor: Makoto KANEYASU
  • Patent number: 8994439
    Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Kaneyasu, Kouhei Toyotaka
  • Patent number: 8928708
    Abstract: An object is to suppress crosstalk. A display device includes a pixel portion which includes a first display region, a second display region, and a non-light-emitting region provided between the first display region and the second display region; and a parallax barrier which includes a first light control region, a second light control region, and a light-transmitting region provided between the first light control region and the second light control region. The first light control region overlaps with the first display region, the second light control region overlaps with the second display region, and the center of the width of the light-transmitting region overlaps with the non-light-emitting region.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hiroyuki Miyake, Kouhei Toyotaka, Hikaru Harada, Makoto Kaneyasu
  • Patent number: 8610482
    Abstract: A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Kaneyasu
  • Publication number: 20130278324
    Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 24, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto KANEYASU, Kouhei TOYOTAKA
  • Publication number: 20130021239
    Abstract: A display device includes a display panel including a plurality of pixels, a shutter panel including a driver circuit, a liquid crystal, and light-transmitting electrodes provided in a striped manner, and a positional data detector configured to detect a positional data of a viewer. The shutter panel is provided over a display surface side of the display panel, a width of one of the light-transmitting electrodes in the shutter panel is smaller than that of one of the plurality of pixels, and the driver circuit in the shutter panel is configured to selectively output signals for forming a parallax barrier to the light-transmitting electrodes. The parallax barrier is capable of changing its shape in accordance with the detected positional data.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 24, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun KOYAMA, Hiroyuki MIYAKE, Hideaki SHISHIDO, Seiko INOUE, Kouhei TOYOTAKA, Koji KUSUNOKI, Hikaru HARADA, Makoto KANEYASU
  • Publication number: 20130016143
    Abstract: An object is to suppress crosstalk. A display device includes a pixel portion which includes a first display region, a second display region, and a non-light-emitting region provided between the first display region and the second display region; and a parallax barrier which includes a first light control region, a second light control region, and a light-transmitting region provided between the first light control region and the second light control region. The first light control region overlaps with the first display region, the second light control region overlaps with the second display region, and the center of the width of the light-transmitting region overlaps with the non-light-emitting region.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 17, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun KOYAMA, Hiroyuki MIYAKE, Kouhei TOYOTAKA, Hikaru HARADA, Makoto KANEYASU
  • Publication number: 20120299639
    Abstract: A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 29, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Kaneyasu