Patents by Inventor Makoto Kiyama
Makoto Kiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170137966Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.Type: ApplicationFiled: April 10, 2015Publication date: May 18, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Patent number: 9647058Abstract: A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q?0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking.Type: GrantFiled: February 4, 2015Date of Patent: May 9, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Takashi Matsuura, Mitsuru Shimazu
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Publication number: 20170101724Abstract: There is provided a gallium nitride substrate having a C plane as a surface with a diameter of not less than 100 mm, the gallium nitride substrate including first regions and second regions having different average values of band-edge emission intensities in a micro photoluminescence mapping at 25° C. in a square region located in the C plane and having sides each having a length of 2 mm, an average value Ibe1a of the band-edge emission intensities of the first regions and an average value Ibe2a of the band-edge emission intensities of the second regions satisfying the following relational expressions (I) and (II): Ibe1a>Ibe2a . . . (I) and 2.1?Ibe1a/Ibe2a?9.4 . . . (II).Type: ApplicationFiled: April 16, 2015Publication date: April 13, 2017Applicant: Sumitomo Electric Industries, Ltd.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Publication number: 20160372609Abstract: A Schottky barrier diode includes a semiconductor layer, a Schottky electrode on a first main surface of the semiconductor layer, the Schottky electrode being in Schottky contact with the semiconductor layer, and an ohmic electrode on a second main surface of the semiconductor layer opposite the first main surface, the ohmic electrode being in ohmic contact with the semiconductor layer. The semiconductor layer contains gallium nitride or silicon carbide. The semiconductor layer includes a drift layer. The drift layer has a thickness of 2 ?m or less.Type: ApplicationFiled: June 17, 2016Publication date: December 22, 2016Inventors: Makoto Kiyama, Masaya Okada, Susumu Yoshimoto, Masaki Ueno
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Patent number: 9312340Abstract: A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate having a thickness ts of 0.1 mm or more and 1 mm or less and a group III nitride film having a thickness tf, thinner than the thickness ts, of 0.01 mm or more and 0.25 mm or less that are bonded to each other. An absolute value |??| of a difference ?? in thermal expansion coefficient determined by subtracting a thermal expansion coefficient ?s of the support substrate from a thermal expansion coefficient ?f of the group III nitride film is 2.2×10?6 K?1 or less. A Young's modulus Es and the thickness ts of the support substrate, a Young's modulus Ef and the thickness tf of the group III nitride film, and the difference ?? in thermal expansion coefficient satisfy a relation: ts2/tf?6Ef·|??|/Es.Type: GrantFiled: September 4, 2014Date of Patent: April 12, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Keiji Ishibashi, Akihiro Hachigo, Naoki Matsumoto, Fumitake Nakanishi
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Publication number: 20150349063Abstract: A group III nitride composite substrate with a diameter of 75 mm or more includes a support substrate having a thickness ts of 0.1 mm or more and 1 mm or less and a group III nitride film having a thickness tf, thinner than the thickness ts, of 0.01 mm or more and 0.25 mm or less that are bonded to each other. An absolute value |??| of a difference ?? in thermal expansion coefficient determined by subtracting a thermal expansion coefficient ?s of the support substrate from a thermal expansion coefficient ?f of the group III nitride film is 2.2×10?6 K?1 or less. A Young's modulus Es and the thickness ts of the support substrate, a Young's modulus Ef and the thickness tf of the group III nitride film, and the difference ?? in thermal expansion coefficient satisfy a relation: ts2/tf?6Ef·|??|/Es.Type: ApplicationFiled: September 4, 2014Publication date: December 3, 2015Inventors: Makoto KIYAMA, Keiji ISHIBASHI, Akihiro HACHIGO, Naoki MATSUMOTO, Fumitake NAKANISHI
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Publication number: 20150221780Abstract: A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25° C., a product R•Q of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of R•Q?0.24×Vblocking2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage Vblocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to Vblocking.Type: ApplicationFiled: February 4, 2015Publication date: August 6, 2015Inventors: Makoto KIYAMA, Takashi MATSUURA, Mitsuru SHIMAZU
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Patent number: 8981428Abstract: There are provided a semiconductor device in which a drain leak current can be reduced in the transistor operation while high vertical breakdown voltage is achieved and a method for producing the semiconductor device. In the semiconductor device, an opening 28 that extends from an n+-type contact layer 8 and reaches an n-type drift layer 4 through a p-type barrier layer 6 is formed. The semiconductor device includes a regrown layer 27 located so as to cover portions of the p-type barrier layer 6 and the like that are exposed to the opening, the regrown layer 27 including an undoped GaN channel layer 22 and a carrier supply layer 26; an insulating layer 9 located so as to cover the regrown layer 27; and a gate electrode G located on the insulating layer 9. In the p-type barrier layer, the Mg concentration A (cm?3)and the hydrogen concentration B (cm?3) satisfy 0.1<B/A<0.9 . . . (1).Type: GrantFiled: July 6, 2011Date of Patent: March 17, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Masaya Okada, Masaki Ueno, Makoto Kiyama
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Patent number: 8969920Abstract: A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.Type: GrantFiled: July 6, 2011Date of Patent: March 3, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Masaki Ueno, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
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Patent number: 8941174Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.Type: GrantFiled: October 17, 2011Date of Patent: January 27, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
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Patent number: 8901698Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.Type: GrantFiled: July 3, 2013Date of Patent: December 2, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
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Patent number: 8896058Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.Type: GrantFiled: October 5, 2011Date of Patent: November 25, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
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Patent number: 8890239Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.Type: GrantFiled: July 26, 2011Date of Patent: November 18, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
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Patent number: 8884306Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.Type: GrantFiled: January 19, 2012Date of Patent: November 11, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Kyono, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama
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Patent number: 8816398Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.Type: GrantFiled: July 6, 2011Date of Patent: August 26, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
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Patent number: 8815716Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.Type: GrantFiled: November 19, 2013Date of Patent: August 26, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku Horii
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Publication number: 20140203329Abstract: Provided is a nitride electronic device having a structure that allows the reduction of leakage by preventing the carrier concentration from increasing in a channel layer. An inclined surface and a primary surface of a semiconductor stack extend along first and second reference planes R1, R2, respectively. The primary surface of the stack is inclined at an angle ranging from 5 to 40 degrees with respect to a reference axis indicating a c-axis direction of hexagonal group III nitride. An axis normal to the plane R1 and the axis form an angle smaller than the angle an axis normal to the plane R2 and the axis form. The oxygen concentration of the channel layer is lower than 1×1017 cm?3. It becomes possible to avoid increase in carrier concentration of the channel layer caused by the oxygen addition, thereby reducing leakage current via the channel layer in the transistor.Type: ApplicationFiled: June 3, 2011Publication date: July 24, 2014Applicant: Summitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Masaya Okada, Yusuke Yoshizumi, Makoto Kiyama, Masaki Ueno, Koji Katayama, Takao Nakamura
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Patent number: 8729562Abstract: There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 15 having an opening 28, a regrown layer 27 including a channel, a gate electrode G, a source electrode S, and a drain electrode D. The regrown layer 27 includes an electron transit layer 22 and an electron supply layer 26. The GaN-based layered body includes a p-type GaN layer 6 whose end surface is covered by the regrown layer in the opening, and a p-side electrode 11 that is in ohmic contact with the p-type GaN layer is disposed.Type: GrantFiled: June 24, 2010Date of Patent: May 20, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masaya Okada, Makoto Kiyama
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Publication number: 20140110758Abstract: The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.Type: ApplicationFiled: June 8, 2011Publication date: April 24, 2014Applicant: Sumitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Masaya Okada, Masaki Ueno, Makoto Kiyama
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Publication number: 20140080292Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: Sumitomo Electric Industries, Ltd.Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku HORII