Patents by Inventor Makoto Kiyama
Makoto Kiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7732236Abstract: The invention provides Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.Type: GrantFiled: May 13, 2005Date of Patent: June 8, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Hideaki Nakahata, Koji Uematsu, Makoto Kiyama, Youichi Nagai, Takao Nakamura
-
Patent number: 7687822Abstract: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 ?·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.Type: GrantFiled: March 27, 2007Date of Patent: March 30, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumu Yoshimoto
-
Publication number: 20100059761Abstract: A Schottky barrier diode includes a GaN freestanding substrate having a front surface, a GaN epitaxial layer deposited on the front surface, and an insulation layer deposited on the GaN epitaxial layer at a front surface and having an opening. Furthermore, the Schottky barrier diode also includes an electrode. The electrode is configured by a Schottky electrode provided in the opening in contact with the GaN epitaxial layer, and a field plate electrode connected to the Schottky electrode and also overlapping the insulation layer. The GaN freestanding substrate has a dislocation density of at most 1×108 cm?2.Type: ApplicationFiled: August 22, 2008Publication date: March 11, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
-
Publication number: 20090194796Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm?3 or more. The donor impurity is at least either silicon or germanium.Type: ApplicationFiled: March 1, 2006Publication date: August 6, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Makoto Kiyama, Tatsuya Tanabe, Kouhei Miura, Takashi Sakurada
-
Publication number: 20090189186Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1?YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1?YN epitaxial layer (O<Y?1). A Schottky electrode 19 is provided on the AlYGa1?YN epitaxial layer 15. The Schottky electrode 19 constitutes a gate electrode of the high electron mobility transistor 11. The source electrode 21 is provided on the gallium nitride epitaxial layer 15. The drain electrode 23 is provided on the gallium nitride epitaxial layer 15.Type: ApplicationFiled: March 6, 2006Publication date: July 30, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsuya Tanabe, Kouhei Miura, Makoto Kiyama, Takashi Sakurada
-
Publication number: 20090189190Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: ApplicationFiled: March 3, 2006Publication date: July 30, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
-
Patent number: 7531889Abstract: In a Schottky diode 11, a gallium nitride support base 13 includes a first surface 13a and a second surface 13b opposite from the first surface and has a carrier concentration exceeding 1×1018 cm?3. A gallium nitride epitaxial layer 15 is disposed on the first surface 13a. An Ohmic electrode 17 is disposed on the second surface 13b. The Schottky electrode 19 is disposed on the gallium nitride epitaxial layer 15. A thickness D1 of the gallium nitride epitaxial layer 15 is at least 5 microns and no more than 1000 microns. Also, the carrier density of the gallium nitride epitaxial layer 15 is at least 1×1014 cm?3 and no more than 1×1017 cm?3.Type: GrantFiled: September 1, 2005Date of Patent: May 12, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Takuji Okahisa, Takashi Sakurada
-
Publication number: 20090108297Abstract: A method of manufacturing a semi-insulating nitride semiconductor substrate includes the steps of forming on an underlying substrate, a mask in which dotted or striped coating portions having a width or a diameter Ds from 10 ?m to 100 ?m are arranged at an interval Dw from 250 ?m to 2000 ?m, growing a nitride semiconductor crystal on the underlying substrate with an HVPE method at a growth temperature from 1040° C. to 1150° C. by supplying a group III raw material gas and a group V raw material gas of which group V/group III ratio R5/3 is set to 1 to 10 and a gas containing iron, and removing the underlying substrate, to thereby obtain a free-standing semi-insulating nitride semiconductor substrate having a specific resistance not smaller than 1×105 ?cm and a thickness not smaller than 100 ?m. Thus, the semi-insulating nitride semiconductor crystal substrate in which warpage is less and cracking is less likely can be obtained.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Fumitaka SATO, Seiji NAKAHATA, Makoto KIYAMA
-
Publication number: 20080315209Abstract: Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode (11) consists of a Group III nitride support substrate (13), a gallium nitride region (15), and a Schottky electrode (17). The Group III nitride support substrate (13) has electrical conductivity. The Schottky electrode (17) forms a Schottky junction on the gallium nitride region (15). The gallium nitride region (15) is fabricated on a principal face (13a) of the Group III nitride support substrate (13). The gallium nitride region (15) has a (10 12)-plane XRD full-width-at-half-maximum of 100 sec or less.Type: ApplicationFiled: January 20, 2006Publication date: December 25, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kouhei Miura, Makoto Kiyama, Takashi Sakurada
-
Publication number: 20080265258Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor 1, a supporting substrate 3 is composed of AlN, AlGaN, or GaN. An AlyGa1-yN epitaxial layer 5 has a surface roughness (RMS) of 0.25 mm or less, wherein the surface roughness is defined by a square area measuring 1 ?m per side. A GaN epitaxial layer 7 is provided between the AlyGa1-yN supporting substrate 3 and the AlyGa1-yN epitaxial layer 5. A Schottky electrode 9 is provided on the AlyGa1-yN epitaxial layer 5. A first ohmic electrode 11 is provided on the AlyGa1-yN epitaxial layer 5. A second ohmic electrode 13 is provided on the AlyGa1-yN epitaxial layer 5. One of the first and second ohmic electrodes 11 and 13 constitutes a source electrode, and the other constitutes a drain electrode. The Schottky electrode 9 constitutes a gate electrode of the high electron mobility transistor 1.Type: ApplicationFiled: March 3, 2006Publication date: October 30, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tatsuya Tanabe, Makoto Kiyama, Kouhei Miura, Takashi Sakurada
-
Publication number: 20080210959Abstract: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 ?·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.Type: ApplicationFiled: March 27, 2007Publication date: September 4, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumu Yoshimoto
-
Publication number: 20080128706Abstract: Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 ?m2 or more being D cm?2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.Type: ApplicationFiled: November 29, 2007Publication date: June 5, 2008Applicant: Sumitomo Electric Industries, Ltd.Inventors: Shinsuke Fujiwara, Takashi Sakurada, Makoto Kiyama, Yusuke Yoshizumi
-
Publication number: 20070164306Abstract: The invention provides Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 ?m or more but 600 ?m or less in thickness, and is 0.2 mm or more but 50 mm or less in width.Type: ApplicationFiled: May 13, 2005Publication date: July 19, 2007Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Hideaki Nakahata, Koji Uematsu, Makoto Kiyama, Youichi Nagai, Takao Nakamura
-
Patent number: 7202509Abstract: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 ?·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.Type: GrantFiled: August 23, 2004Date of Patent: April 10, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumu Yoshimoto
-
Patent number: 7195937Abstract: A measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized. In a method of measuring the breakdown voltage of a semiconductor epitaxial wafer having to do with the present invention, the breakdown voltage between contacts 14 and 18 is measured only through the Schottky contacts, without need for ohmic contacts. Inasmuch as the manufacturing process of forming ohmic contacts is accordingly omitted, the semiconductor epitaxial wafer 10 may be readily used in a breakdown-voltage measurement test. The measurement of the wafer-10 breakdown voltage thus may be readily carried out. Likewise, because the inter-contact breakdown voltage V2 of a wafer 10 can be measured prior to manufacturing a working device from it, unsuitable wafers 10 can be excluded before they are cycled through the working-device fabrication process.Type: GrantFiled: January 23, 2003Date of Patent: March 27, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Masashi Yamashita, Makoto Kiyama
-
Patent number: 7190004Abstract: A light emitting device includes a nitride semiconductor substrate with a resistivity of 0.5 ?·cm or less, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at a first main surface side of the nitride semiconductor substrate, and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein one of the nitride semiconductor substrate and the p-type nitride semiconductor layer is mounted at the top side which emits light and the other is placed at the down side, and a single electrode is placed at the top side. Therefore, there is provided a light emitting device which has a simple configuration thereby making it easy to fabricate, can provide a high light emission efficiency for a long time period, and can be easily miniaturized.Type: GrantFiled: December 2, 2004Date of Patent: March 13, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumu Yoshimoto
-
Publication number: 20060046331Abstract: In a Schottky diode 11, a gallium nitride support base 13 includes a first surface 13a and a second surface 13b opposite from the first surface and has a carrier concentration exceeding 1×1018 cm?3. A gallium nitride epitaxial layer 15 is disposed on the first surface 13a. An Ohmic electrode 17 is disposed on the second surface 13b. The Schottky electrode 19 is disposed on the gallium nitride epitaxial layer 15. A thickness D1 of the gallium nitride epitaxial layer 15 is at least 5 microns and no more than 1000 microns. Also, the carrier density of the gallium nitride epitaxial layer 15 is at least 1×1014 cm?3 and no more than 1×1017 cm?3.Type: ApplicationFiled: September 1, 2005Publication date: March 2, 2006Applicant: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Takuji Okahisa, Takashi Sakurada
-
Publication number: 20050121688Abstract: A light emitting device includes a nitride semiconductor substrate with a resistivity of 0.5 ?·cm or less, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at a first main surface side of the nitride semiconductor substrate, and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein one of the nitride semiconductor substrate and the p-type nitride semiconductor layer is mounted at the top side which emits light and the other is placed at the down side, and a single electrode is placed at the top side. Therefore, there is provided a light emitting device which has a simple configuration thereby making it easy to fabricate, can provide a high light emission efficiency for a long time period, and can be easily miniaturized.Type: ApplicationFiled: December 2, 2004Publication date: June 9, 2005Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumu Yoshimoto
-
Publication number: 20050118736Abstract: A measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized. In a method of measuring the breakdown voltage of a semiconductor epitaxial wafer having to do with the present invention, the breakdown voltage between contacts 12, 12 is measured only through the Schottky contacts, without need for ohmic contacts. Inasmuch as the manufacturing process of forming ohmic contacts is accordingly omitted, the semiconductor epitaxial wafer 10 may be readily used in a breakdown-voltage measurement test. The measurement of the wafer 10 breakdown voltage thus may be readily carried out. Likewise, because the inter-contact breakdown voltage V2 of a wafer 10 can be measured prior to manufacturing a working device from it, unsuitable wafers 10 can be excluded before they are cycled through the working-device fabrication process.Type: ApplicationFiled: January 23, 2003Publication date: June 2, 2005Inventors: Katsushi Akita, Masashi Yamashita, Makoto Kiyama
-
Publication number: 20050062060Abstract: In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 ?·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.Type: ApplicationFiled: August 23, 2004Publication date: March 24, 2005Inventors: Youichi Nagai, Makoto Kiyama, Takao Nakamura, Takashi Sakurada, Katsushi Akita, Koji Uematsu, Ayako Ikeda, Koji Katayama, Susumui Yoshimoto