Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.

Abstract: An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

Abstract: According to the present invention, a serial/parallel converter, which outputs, with the same phase and in parallel, a plurality of data sets input serially in synchronization with an input clock, comprises: at least two input latch flip-flops for latching the plurality of input data sets in synchronization with the input clock; a pulse generator for generating a plurality of latch clocks synchronously with timings at which the plurality of data sets are held by the input latch flip-flops; a plurality of holding flip-flips for latching in order the plurality of data sets held by the input latch flip-flops in accordance with the plurality of latch clocks; and a plurality of output latch flip-flops for, in accordance with the last latch clock synchronous with when the last data set of the plurality of data sets is held by the input latch flip-flops, latching in parallel the plurality of data sets held by the holding flip-flops and the last data set by the input latch flip-flops.