Patents by Inventor Makoto Koga

Makoto Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6034555
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
  • Patent number: 5936897
    Abstract: The present invention relates to a memory device including a sense amplifier for driving bit line pair and write amplifier for driving data bus line connecting to the bit line pair. According to the present invention, when the column gates are opened and the sense amplifiers are connected to the data bus amplifiers via the data bus pair, one sense amplifier circuit portion of each sense amplifier is deactivated and the conflicts which arise from the operation of the write amplifiers in the data bus amplifiers and of the sense amplifiers can be avoided, and the writing operation can be performed at a high speed. In addition, the control of the sense amplifiers need not be changed either for the reading process or for the writing process, and the writing speed can be increased without the reading being affected.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventor: Makoto Koga
  • Patent number: 5838604
    Abstract: A semiconductor memory device includes a plurality of bit lines, first sense amplifiers each connected to a corresponding one of the plurality of bit lines, and a first data bus laid out in parallel to the plurality of bit lines and connected to the plurality of bit lines via gates and the first sense amplifiers. The semiconductor memory device further includes column-selection lines laid out perpendicularly to the plurality of bit lines to open at least one of the gates to connect the first data bus to the plurality of bit lines.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: November 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Hironobu Tsuboi, Yoshinori Okajima, Tsuyoshi Higuchi, Makoto Koga
  • Patent number: 5557221
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: September 17, 1996
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga