Patents by Inventor Makoto Miyamura
Makoto Miyamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170256587Abstract: A purpose of the invention is to provide a crossbar switch for reducing the layout areas of a crossbar switch and peripheral circuits thereof. A crossbar switch of the invention comprises: a plurality of first wires extending in a first direction; a plurality of second wires extending in a second direction; a plurality of third wires extending in a third direction; a plurality of fourth wires extending in a fourth direction; and a plurality of switch cells connected to the first and second wires. The first wires are skew relative to the second and fourth wires, while the third wires are skew relative to the second and fourth wires. The switch cells are connected to the third and fourth wires, and further, the third wires are also connected to the switch cells connected to the first wires adjacent to the respective first wires; or alternatively, further, the fourth wires are also connected to the switch cells connected to the second wires adjacent to the respective second wires.Type: ApplicationFiled: September 11, 2015Publication date: September 7, 2017Applicant: NEC CorporationInventors: Yukihide TSUJI, Xu BAI, Makoto MIYAMURA, Toshitsugu SAKAMOTO, Munehiro TADA
-
Patent number: 9754998Abstract: A semiconductor device, includes first, second, and third switching elements. The third switching element comprises first and second terminals. Each of the first and second switching elements comprise a unified ion conductor, a first electrode disposed to contact the ion conductor and supply metal ions thereto, and a second electrode disposed to contact the ion conductor and is less susceptible to ionization than the first electrode. The first electrodes of the first switching element and the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected, or the second electrode of the first switching element and the second electrode of the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the second electrodes which are electrically connected.Type: GrantFiled: May 12, 2015Date of Patent: September 5, 2017Assignee: NEC CORPORATIONInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Patent number: 9692422Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.Type: GrantFiled: February 27, 2015Date of Patent: June 27, 2017Assignee: NEC CorporationInventors: Ryusuke Nebashi, Makoto Miyamura, Noboru Sakimura, Yukihide Tsuji, Ayuka Tada
-
Publication number: 20170070228Abstract: In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires.Type: ApplicationFiled: February 27, 2015Publication date: March 9, 2017Inventors: Ryusuke NEBASHI, Makoto MIYAMURA, Noboru SAKIMURA, Yukihide TSUJI, Ayuka TADA
-
Patent number: 9548115Abstract: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second electrodes have corner portions, respectively, and the distance between the corner portions of the first and the second electrodes is set equal to the shortest distance between the first and the second electrodes. Furthermore, the variable resistance element has a third electrode, which is disposed on the one surface of the variable resistance film.Type: GrantFiled: March 14, 2013Date of Patent: January 17, 2017Assignee: NEC CORPORATIONInventors: Munehiro Tada, Toshitsugu Sakamoto, Makoto Miyamura
-
Patent number: 9508432Abstract: This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a fourth terminal, and which forms an intermediate node (105) by having the third terminal connected to the second terminal, and has the resistance state thereof varied when an applied voltage exceeds a reference value; first wiring (101) connected to the first terminal; second wiring (102), which is connected to the fourth terminal, and which extends in the direction intersecting the first wiring (101) in a planar view; a first selection switch element (106) connected to the first wiring (101); and a second selection switch element (107) connected to the second wiring (102).Type: GrantFiled: February 28, 2013Date of Patent: November 29, 2016Assignee: NEC CORPORATIONInventors: Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada
-
Publication number: 20150318473Abstract: A semiconductor device, includes first, second, and third switching elements. The third switching element comprises first and second terminals. Each of the first and second switching elements comprise a unified ion conductor, a first electrode disposed to contact the ion conductor and supply metal ions thereto, and a second electrode disposed to contact the ion conductor and is less susceptible to ionization than the first electrode. The first electrodes of the first switching element and the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected, or the second electrode of the first switching element and the second electrode of the second switching element are electrically connected. The first terminal of the third switching element is electrically connected to only the second electrodes which are electrically connected.Type: ApplicationFiled: May 12, 2015Publication date: November 5, 2015Inventors: Munehiro TADA, Makoto Miyamura, Hiromitsu Hada
-
Patent number: 9059082Abstract: A semiconductor device includes a first switching element, a second switching element, and at least one third switching element; wherein the third switching element includes a first terminal and a second terminal, wherein each of the first switching element and the second switching element includes an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein (a) the first electrode of the first switching element and the first electrode of the second switching element are electrically connected each other, and the first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected each other or (b) the second electrode of the first switching element and the second electrode of the second switching eleType: GrantFiled: June 9, 2011Date of Patent: June 16, 2015Assignee: NEC CorporationInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Publication number: 20150131358Abstract: This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a fourth terminal, and which forms an intermediate node (105) by having the third terminal connected to the second terminal, and has the resistance state thereof varied when an applied voltage exceeds a reference value; first wiring (101) connected to the first terminal; second wiring (102), which is connected to the fourth terminal, and which extends in the direction intersecting the first wiring (101) in a planar view; a first selection switch element (106) connected to the first wiring (101); and a second selection switch element (107) connected to the second wiring (102).Type: ApplicationFiled: February 28, 2013Publication date: May 14, 2015Inventors: Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada
-
Patent number: 9029825Abstract: A semiconductor device includes multilayer interconnects and two variable resistance elements (22a, 22b) that are provided among the multilayer interconnects and that include first electrodes (5), second electrodes (10a, 10b), and variable resistance element films (9a, 9b) that are each interposed between first electrodes (5) and respective second electrodes (10a, 10b). Either the first electrodes (5) or the second electrodes (10a, 10b) of the two variable resistance elements (22a, 22b) are unified.Type: GrantFiled: June 14, 2011Date of Patent: May 12, 2015Assignee: NEC CorporationInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Publication number: 20150103583Abstract: This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable resistance film, and a second electrode, which is disposed in contact with the other surface of the variable resistance film. The first and the second electrodes have corner portions, respectively, and the distance between the corner portions of the first and the second electrodes is set equal to the shortest distance between the first and the second electrodes. Furthermore, the variable resistance element has a third electrode, which is disposed on the one surface of the variable resistance film.Type: ApplicationFiled: March 14, 2013Publication date: April 16, 2015Applicant: NEC CORPORATIONInventors: Munehiro Tada, Toshitsugu Sakamoto, Makoto Miyamura
-
Publication number: 20150048680Abstract: A semiconductor device includes a current control unit whose conductance is variable and a control unit configured to control the conductance of the current control unit. The current control unit is connected to a direct current power source in parallel with a load for the direct current power source, through a capacitor. The control unit sets the current control unit to a first conductance when the direct current power source and the load are not in a conduction state, and sets the current control unit to a second conductance larger than the first conductance when the direct current power source and the load are in the conduction state.Type: ApplicationFiled: March 28, 2013Publication date: February 19, 2015Inventors: Makoto Miyamura, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Tadahiko Sugibayashi
-
Patent number: 8816312Abstract: A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element.Type: GrantFiled: September 20, 2011Date of Patent: August 26, 2014Assignee: NEC CorporationInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Publication number: 20130181180Abstract: A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element.Type: ApplicationFiled: September 20, 2011Publication date: July 18, 2013Inventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Publication number: 20130092895Abstract: A semiconductor device includes a first switching element, a second switching element, and at least one third switching element; wherein the third switching element includes a first terminal and a second terminal, wherein each of the first switching element and the second switching element includes an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein (a) the first electrode of the first switching element and the first electrode of the second switching element are electrically connected each other, and the first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected each other or (b) the second electrode of the first switching element and the second electrode of the second switching eleType: ApplicationFiled: June 9, 2011Publication date: April 18, 2013Applicant: NEC CorporationInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Publication number: 20130082231Abstract: A semiconductor device includes multilayer interconnects and two variable resistance elements (22a, 22b) that are provided among the multilayer interconnects and that include first electrodes (5), second electrodes (10a, 10b), and variable resistance element films (9a, 9b) that are each interposed between first electrodes (5) and respective second electrodes (10a, 10b). Either the first electrodes (5) or the second electrodes (10a, 10b) of the two variable resistance elements (22a, 22b) are unified.Type: ApplicationFiled: June 14, 2011Publication date: April 4, 2013Applicant: NEC CorporationInventors: Munehiro Tada, Makoto Miyamura, Hiromitsu Hada
-
Patent number: 7964921Abstract: To provide a MOSFET which is increased in substrate bias effect ? without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a semiconductor substrate (101) and an insulating film (103); a sidewall insulating film (106) covering the side surface of the gate electrode (104); and source/drain regions surrounded by the sidewall insulating film (106) and a shallow trench isolation (102) in a self-alignment manner, in which an impurity concentration of a first conductivity type which is the same type as a well-forming impurity has a profile becoming, in a lower direction of the gate electrode (104), lower in a channel formation region, then higher and again lower, and a high-concentration first conductivity type impurity region (110) is provided, in which the impurity concentration of the first conductivity type is formed to be low in the source/drain regions and to be high below the gate electrode (104) sandwiched between the source/drain regions.Type: GrantFiled: August 22, 2006Date of Patent: June 21, 2011Assignee: Renesas Electronics CorporationInventor: Makoto Miyamura
-
Publication number: 20090321849Abstract: A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness.Type: ApplicationFiled: May 23, 2007Publication date: December 31, 2009Applicant: NEC CORPORATIONInventors: Makoto Miyamura, Kiyoshi Takeuchi
-
Publication number: 20090250771Abstract: To provide a MOSFET which is increased in substrate bias effect ? without increasing parasitic capacitance and junction leak current, the MOSFET includes: a gate electrode (104) formed on a semiconductor substrate (101) and an insulating film (103); a sidewall insulating film (106) covering the side surface of the gate electrode (104); and source/drain regions surrounded by the sidewall insulating film (106) and a shallow trench isolation (102) in a self-alignment manner, in which an impurity concentration of a first conductivity type which is the same type as a well-forming impurity has a profile becoming, in a lower direction of the gate electrode (104), lower in a channel formation region, then higher and again lower, and a high-concentration first conductivity type impurity region (110) is provided, in which the impurity concentration of the first conductivity type is formed to be low in the source/drain regions and to be high below the gate electrode (104) sandwiched between the source/drain regions.Type: ApplicationFiled: August 22, 2006Publication date: October 8, 2009Applicant: NEC CORPORATONInventor: Makoto Miyamura
-
Patent number: 7138553Abstract: Tetrachloroethylene containing a stabilizer is contacted with a zeolite having an average pore size of 3.4 to 11 ? and/or a carbonaceous adsorbent having an average pore size of 3.4 to 11 ? in a liquid phase to obtain a high purity tetrachloroethylene. A halogenated alkene and/or a halogenated alkane are reacted with hydrogen fluoride in the presence of a fluorination catalyst to produce a first hydrofluorocarbon, a halogenated alkene and/or a halogenated alkane are reacted with hydrogen fluoride in the presence of a fluorination catalyst to produce a second hydrofluorocarbon, and the products are joined and then distilled to obtain the first and second hydrofluorocarbons.Type: GrantFiled: July 5, 2002Date of Patent: November 21, 2006Assignee: Showa Denko K.K.Inventors: Hiromoto Ohno, Toshio Ohi, Makoto Miyamura