Patents by Inventor Makoto Mizukami

Makoto Mizukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10814488
    Abstract: To hold a long member in the original shape of the long member at a precise position, a long member assembling device has: a plurality of hand parts configured to grip a long member; arm parts and trunk parts configured to move the hand parts to adjust the positions of the plurality of hand parts gripping the long member; a storage unit in which the original shape of the long member is stored; and a control unit configured to, on the basis of the original shape of the long member stored in the storage unit, drive the arm parts and the trunk parts to adjust the positions of the plurality of hand parts gripping the long member such that the shape of the long member gripped by the plurality of hand parts matches the original shape of the long member stored in the storage unit.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 27, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Toshihiro Tombe, Takuya Goto, Takahiro Inagaki, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
  • Patent number: 10734483
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 4, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Makoto Mizukami, Masaru Furukawa, Teruyuki Ohashi
  • Patent number: 10668583
    Abstract: In order to hold a long member without using a fixing jig and without deforming the long member in holding the long member, a long member assembling device is provided with: multiple hand parts for gripping a long member; and arm parts and trunk parts for moving the hand parts to adjust the positions of the hand parts gripping the long member. The hand parts have a configuration such that, when the positions thereof are adjusted by the arm parts and the trunk parts, the hand parts are capable of moving in the longitudinal direction of the long member while gripping the long member.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 2, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takahiro Inagaki, Toshihiro Tombe, Takuya Goto, Makoto Hirai, Naoki Goto, Masanobu Mizukami, Katsumi Nakamura
  • Publication number: 20200168546
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 28, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
  • Publication number: 20200091296
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.
    Type: Application
    Filed: February 19, 2019
    Publication date: March 19, 2020
    Inventors: Makoto Mizukami, Masaru Furukawa, Teruyuki Ohashi
  • Publication number: 20200091334
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; first and second trenches extending in a first direction; first and second gate electrodes; a first silicon carbide region of a first conductivity type; a plurality of second silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane, located between the first trench and the second trench, and separated from each other in the first direction; a fourth silicon carbide region of the second conductivity type between two of the second silicon carbide regions and contacting the second silicon carbide region; a fifth silicon carbide region of the second conductivity type between the two second silicon carbide regions and contacting the second silicon carbide region; a first electrode contacting the first silicon carbide region; and a second electrode.
    Type: Application
    Filed: February 19, 2019
    Publication date: March 19, 2020
    Inventors: Makoto Mizukami, Takuma Suzuki, Yujiro Hara
  • Patent number: 10535604
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 10297685
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of third electrodes, and a plurality of gate electrodes. The gate electrodes and the third electrodes are arranged parallel in a second direction and periodically with a third arrangement cycle such that the ratio of the number of the gate electrodes and the third electrodes in the first region is m3 to m4 (m3, m4 being positive integers and m3 being more than or equal to m4).
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Makoto Mizukami
  • Publication number: 20190088774
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of third electrodes, and a plurality of gate electrodes. The gate electrodes and the third electrodes are arranged parallel in a second direction and periodically with a third arrangement cycle such that the ratio of the number of the gate electrodes and the third electrodes in the first region is m3 to m4 (m3, m4 being positive integers and m3 being more than or equal to m4).
    Type: Application
    Filed: March 8, 2018
    Publication date: March 21, 2019
    Inventor: Makoto Mizukami
  • Publication number: 20180301415
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 10056333
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Publication number: 20170194260
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
  • Patent number: 9640547
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Publication number: 20170077038
    Abstract: A semiconductor device includes a first identification mark that is identifiable by a photoluminescence method, and a second identification mark that is identifiable using visible light.
    Type: Application
    Filed: March 7, 2016
    Publication date: March 16, 2017
    Inventors: Makoto MIZUKAMI, Junichi UEHARA
  • Publication number: 20160276497
    Abstract: A semiconductor device includes a SiC substrate having first and second surfaces, p-type first SiC areas on the first surface of the SiC substrate, an n-type second SiC area between the first SiC areas and the second surface, a third SiC area having an n-type dopant concentration higher than that of the second SiC area, on the second surface of the SiC substrate, a first electrode on the first surface and electrically connected to the first SiC areas, and a second electrode on the second surface and electrically connected to the third SiC area. Where the area between the first SiC areas and the second surface is a first area, and the area between a portion between adjacent first SiC areas and the second surface is set as a second area, a Z1/2 level density of the first area is higher than that of the second area.
    Type: Application
    Filed: August 31, 2015
    Publication date: September 22, 2016
    Inventor: Makoto MIZUKAMI
  • Patent number: 9437682
    Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Takashi Shinohe, Makoto Mizukami
  • Publication number: 20160197035
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 7, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
  • Patent number: 9337035
    Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type located between the first electrode and the second electrode and having a region in which a carbon vacancy density becomes lower in a first direction from the first electrode to the second electrode, a second semiconductor layer of the first conductivity type located between the first electrode and the first semiconductor layer and having an impurity element concentration higher than the impurity element concentration of the first semiconductor layer, and a plurality of third semiconductor layers of a second conductivity type located between the second electrode and the first semiconductor layer.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Mizukami, Takuma Suzuki
  • Patent number: 9257388
    Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: February 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Mizukami, Takeshi Kamigaichi
  • Patent number: 9236434
    Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio