Patents by Inventor Makoto Mizukami
Makoto Mizukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140335684Abstract: A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants.Type: ApplicationFiled: February 28, 2014Publication date: November 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto MIZUKAMI, Naoko YANASE, Atsuko YAMASHITA
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Publication number: 20140306239Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Makoto MIZUKAMI
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Publication number: 20140284618Abstract: An aspect of the present embodiment, there is provided a semiconductor device, including a first electrode, a first semiconductor layer having a first conductive type connected to the first electrode, a second semiconductor layer having a second conductive type contacted to the first semiconductor layer, a third semiconductor layer having the first conductive type, an impurity concentration of the third semiconductor layer being smaller than an impurity concentration of the second semiconductor layer, the third semiconductor layer contacting to the second semiconductor layer to be separated from the first semiconductor layer by the second semiconductor layer, a gate insulator provided on the second semiconductor layer, and the first semiconductor layer and the third semiconductor layer arranged at both sides of the second semiconductor layer, respectively, a gate electrode on the gate insulator; and a second electrode connected to the third semiconductor layer.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Makoto Mizukami
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Patent number: 8841741Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.Type: GrantFiled: September 7, 2011Date of Patent: September 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masamu Kamaga, Makoto Mizukami, Takashi Shinohe
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Patent number: 8841683Abstract: A semiconductor rectifier device includes a semiconductor substrate of a first conductive type of a wide gap semiconductor; a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 ?m or more; a first semiconductor region of the first conductive type of the wide gap semiconductor formed at the semiconductor layer surface; a plurality of second semiconductor regions of a second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of each of the second semiconductor regions is 15 ?m or more; a first electrode formed on the first and second semiconductor regions; and a second electrode formed on a lower surface of the semiconductor substrate.Type: GrantFiled: August 29, 2011Date of Patent: September 23, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Makoto Mizukami
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Patent number: 8835934Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.Type: GrantFiled: March 7, 2012Date of Patent: September 16, 2014Assignee: Kabushiki Kaishia ToshibaInventor: Makoto Mizukami
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Patent number: 8823148Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substraType: GrantFiled: February 24, 2011Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio
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Publication number: 20140217611Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.Type: ApplicationFiled: April 14, 2014Publication date: August 7, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
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Patent number: 8742586Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.Type: GrantFiled: October 18, 2013Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Takeshi Kamigaichi
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Patent number: 8664108Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.Type: GrantFiled: November 17, 2010Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Takeshi Kamigaichi
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Publication number: 20140042620Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.Type: ApplicationFiled: October 18, 2013Publication date: February 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto MIZUKAMI, Takeshi KAMIGAICHI
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Patent number: 8648447Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.Type: GrantFiled: March 1, 2012Date of Patent: February 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Masamu Kamaga, Kazuto Takao
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Publication number: 20130313573Abstract: A semiconductor rectifier includes a first conductivity type wide bandgap semiconductor substrate having a first conductivity type wide bandgap semiconductor layer on an upper surface of which is formed a plurality of first wide bandgap semiconductor regions of the first conductivity type sandwiching a plurality of second wide bandgap semiconductor regions of a second conductivity type, and a plurality of third wide bandgap semiconductor regions of the second conductivity type, at least a part of the third wide bandgap semiconductor regions being connected to the second wide bandgap semiconductor regions and each of the third wide bandgap semiconductor regions having a width smaller than that of the second wide bandgap semiconductor regions. A first electrode is formed on the first and second wide bandgap semiconductor regions and a second electrode is formed on a lower surface of the wide bandgap semiconductor substrate.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Makoto MIZUKAMI, Takashi SHINOHE, Johji NISHIO
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Patent number: 8569795Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon caType: GrantFiled: August 25, 2011Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kono, Yukio Nakabayashi, Takashi Shinohe, Makoto Mizukami
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Patent number: 8557695Abstract: According to an aspect of the present invention, there is provided, a nonvolatile semiconductor storage device including: a substrate; a stacked portion that includes a plurality of conductor layers and a plurality of insulation layers alternately stacked on the substrate, at least one layer of the plurality of conductor layers and the plurality of insulation layers forming a marker layer; a charge accumulation film that is formed on an inner surface of a memory plug hole that is formed in the stacked portion from a top surface to a bottom surface thereof; and a semiconductor pillar that is formed inside the memory plug hole through the charge accumulation film.Type: GrantFiled: December 21, 2010Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Fumitaka Arai
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Patent number: 8502237Abstract: A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface ofType: GrantFiled: August 23, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masamu Kamaga, Makoto Mizukami
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Patent number: 8410545Abstract: A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.Type: GrantFiled: February 22, 2010Date of Patent: April 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Hideyuki Funaki
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Patent number: 8269267Abstract: A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.Type: GrantFiled: October 14, 2010Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Fumitaka Arai, Ichiro Mizushima, Makoto Mizukami
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Publication number: 20120228734Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.Type: ApplicationFiled: September 7, 2011Publication date: September 13, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Masamu KAMAGA, Makoto Mizukami, Takashi Shinohe
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Publication number: 20120228635Abstract: A semiconductor rectifier device using an SiC semiconductor at least includes: an anode electrode; an anode area that adjoins the anode electrode and is made of a second conductivity type semiconductor; a drift layer that adjoins the anode area and is made of a first conductivity type semiconductor having a low concentration; a minority carrier absorption layer that adjoins the drift layer and is made of a first conductivity type semiconductor having a higher concentration than that of the drift layer; a high-resistance semiconductor area that adjoins the minority carrier absorption layer, has less thickness than the drift layer and is made of a first conductivity type semiconductor having a concentration lower than that of the minority carrier absorption layer; a cathode contact layer that adjoins the semiconductor area; and a cathode electrode.Type: ApplicationFiled: March 1, 2012Publication date: September 13, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Makoto MIZUKAMI, Masamu Kamaga, Kazuto Takao