Patents by Inventor Makoto Mizukami
Makoto Mizukami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080315280Abstract: A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first gate electrode, the first gate electrode being provided on the single-crystal silicon layer in the first region, and at least one selective gate transistor which has a second gate electrode and is provided on the single-crystal silicon layer in the first region. The one selective gate transistor is provided in such a manner that a part of the second gate electrode is placed on the single-crystal silicon layer in the second region.Type: ApplicationFiled: June 19, 2008Publication date: December 25, 2008Inventors: Shinichi WATANABE, Fumitaka Arai, Makoto Mizukami, Hirofumi Inoue, Masaki Kondo
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Patent number: 7459748Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.Type: GrantFiled: October 16, 2006Date of Patent: December 2, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Fumitaka Arai, Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunoki, Nobutoshi Aoki, Makoto Mizukami, Kiyotaka Miyano, Ichiro Mizushima
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Publication number: 20080253183Abstract: A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.Type: ApplicationFiled: April 2, 2008Publication date: October 16, 2008Inventors: Makoto Mizukami, Kiyohito Nishihara
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Patent number: 7432561Abstract: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.Type: GrantFiled: December 8, 2006Date of Patent: October 7, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Fumitaka Arai
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Publication number: 20080179677Abstract: Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.Type: ApplicationFiled: January 30, 2008Publication date: July 31, 2008Inventors: Takeshi Murata, Makoto Mizukami, Fumitaka Arai
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Publication number: 20080157092Abstract: A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventors: Fumitaka Arai, Ichiro Mizushima, Makoto Mizukami
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Patent number: 7368783Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.Type: GrantFiled: September 21, 2005Date of Patent: May 6, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Takashi Shinohe
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Publication number: 20080073695Abstract: A semiconductor memory including a plurality of cell units arranged in a row direction, each of the cell units includes: a semiconductor region; a first buried insulating film provided on the semiconductor region; a second buried insulating film provided on the first buried insulating film, which has higher dielectric constant than the first buried insulating film; a semiconductor layer provided on the second buried insulating film; and a plurality of memory cell transistors arranged in a column direction, each of the memory cell transistors having a source region, a drain region and a channel region defined in the semiconductor layer.Type: ApplicationFiled: August 20, 2007Publication date: March 27, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Mizukami, Riichiro Shirota, Fumitaka Arai
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Publication number: 20070198766Abstract: A semiconductor memory includes: a first memory cell transistor including: a first floating gate electrode provided on and insulated from the substrate; and a first control gate electrode provided on and insulated from the first floating gate electrode; and a second memory cell transistor including: a second floating gate electrode provided on and insulated from the substrate, an upper surface being larger than a lower surface, and the upper surface being lower than an upper surface of the first floating gate electrode; and a second control gate electrode provided on and insulated from the second floating gate electrode.Type: ApplicationFiled: February 20, 2007Publication date: August 23, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Mizukami, Shigeru Kinoshita, Shigeyuki Takagi
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Publication number: 20070158736Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.Type: ApplicationFiled: December 27, 2006Publication date: July 12, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Fumitaka Arai, Riichiro Shirota, Makoto Mizukami
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Publication number: 20070138576Abstract: An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.Type: ApplicationFiled: December 8, 2006Publication date: June 21, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto MIZUKAMI, Fumitaka ARAI
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Publication number: 20070102749Abstract: A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.Type: ApplicationFiled: October 16, 2006Publication date: May 10, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Fumitaka Arai, Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunokii, Nobutoshi Aoki, Makoto Mizukami, Kiyotaka Miyano, Ichiro Mizushima
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Publication number: 20070023781Abstract: A semiconductor rectifier has a semiconductor layer formed on a substrate, an electric field reduced layer of conductive type contrary to that of the semiconductor layer, which is formed on the semiconductor layer positioned on a bottom portion of a trench formed on a portion of the semiconductor layer, a first electrode connected on the semiconductor layer adjacent to the trench by Schottky junction, a second electrode which is connected on sidewalls of the trench by Schottky junction, electrically conductive with the first electrode and made of a material different from that of the first electrode, and a third electrode formed on the substrate at opposite side of the semiconductor layer.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Mizukami, Takashi Shinohe
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Publication number: 20060267022Abstract: A decrease in breakdown voltage can be prevented as much as possible. A field-effect transistor includes: a drain region made of SiC; a drift layer which is formed on the drain region and is made of n-type SiC; a source region which is formed on the surface of the drift layer and is made of n-type SiC; a channel region which is formed on the surface of the drift layer located on a side of the source region and is made of SiC; an insulating gate which is formed on the channel region; and a p-type base region interposed between the bottom portion of the source region and the drift region, and containing two kinds of p-type impurities.Type: ApplicationFiled: March 8, 2006Publication date: November 30, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Mizukami, Takashi Shinohe
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Publication number: 20060011973Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.Type: ApplicationFiled: September 21, 2005Publication date: January 19, 2006Inventors: Makoto Mizukami, Takashi Shinohe
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Patent number: 6969887Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.Type: GrantFiled: January 21, 2005Date of Patent: November 29, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Mizukami, Takashi Shinohe
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Publication number: 20050161732Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.Type: ApplicationFiled: January 21, 2005Publication date: July 28, 2005Inventors: Makoto Mizukami, Takashi Shinohe
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Patent number: 6479257Abstract: The present invention relates to a method for activating protein wherein protein produced in a biologically inactive form (non-natural-form protein) is converted into a biologically active protein (natural-form protein) by bringing it into contact with cultured cells of an organism, and according to the present invention, the non-natural-form protein can be converted efficiently into the natural-form protein having activity, so the yield of the natural-form protein can be further raised by subjecting, e.g., culture of transformant to the activation treatment.Type: GrantFiled: September 27, 1999Date of Patent: November 12, 2002Assignee: Higeta Shoyu Co., Ltd.Inventors: Akira Miyauchi, Makoto Ozawa, Masato Yoshida, Makoto Mizukami
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Patent number: 5936794Abstract: A media library system capable of carrying out an access to each recording medium in very short time. A media exchange operation is controlled such that the storage cells of the storehouse are divided into at least two groups arranged in an order of average distances with respect to the media drive, including a first group with a shortest average distance with respect to the media drive, and when the previously used recording medium was mounted on the media drive from the first group, the previously used recording medium is stored in the first group, whereas when the previously used recording medium was mounted on the media drive from one group other than the first group, one recording medium with a lowest utilization frequency among an adjacent group of that one group having a shorter average distance with respect to the media drive than that one group is moved from that adjacent group to that one group and then the previously used recording medium is stored in that adjacent group.Type: GrantFiled: October 17, 1995Date of Patent: August 10, 1999Assignee: Nippon Telegraph & Telephone Corp.Inventors: Makoto Mizukami, Nobuyoshi Izawa, Kikuji Katoh, Yoshihiro Isomura, Yoshihiro Sako
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Patent number: 5598385Abstract: A media library system capable of reducing a time and an average moving distance of the media carrying unit required for exchanging the recording media. The system includes a storehouse having a plurality of storage cells for storing a plurality of recording media, a media driving unit for executing data read/write operation with respect to the recording media, and a media carrying unit for carrying the recording media between the storehouse and the media driving unit, so as to exchange a previously used recording medium mounted on the media driving unit with a new recording medium stored in the storehouse.Type: GrantFiled: December 2, 1994Date of Patent: January 28, 1997Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Mizukami, Shigetaro Iwatsu, Masao Sakai, Masahiro Ueno, Nobuyoshi Izawa, Kikuji Katou