Abstract: A circuit layout pattern inspection method and a logical simulator for implementing the same. Wiring is substituted by a .pi. or T equivalent circuit and is described by a nodal equation, and a gate is described by a simplified model, that is, a current source calculation formula. By the nodal equation and the current source calculation formula, a simulation is performed to obtain a delay time for every node. The obtained delay time is stored to make the inspection easy.

Abstract: A logical circuit layout pattern verification method. Verification of a logical circuit layout pattern is performed by: adding the parasitic capacitance of a layout pattern of a logical circuit to a load capacitance of logic gates, calculating an output value of the logical circuit based on the total capacitance, and verifying the layout pattern by comparing the output value and the expected output value calculated at initial design. In the calculation of the delay time of the logic gate, the delay time corresponding to discrete representative values of the load capacitance are first calculated, the functions describing the relationship between the load capacitance and the delay time are calculated using the delay time, and based on the function, the delay time corresponding to the load capacitance having continuous values is calculated. With the method, malfunctioning of the circuit caused by delay time is predictable.