Patents by Inventor Makoto Morino
Makoto Morino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10920664Abstract: An intake manifold is connected to a cylinder of an engine, and extends backward from the cylinder. A throttle body is attached to the intake manifold. As seen in a plan view of an outboard motor, the throttle body is disposed backward of a head cover, while being disposed inward of a lateral end of the intake manifold in a right-and-left direction of the outboard motor.Type: GrantFiled: September 23, 2019Date of Patent: February 16, 2021Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Shinya Maekawa, Makoto Morino, Koichi Nakayama
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Patent number: 10833087Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.Type: GrantFiled: August 21, 2018Date of Patent: November 10, 2020Assignee: Micron Technology, Inc.Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
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Publication number: 20200200075Abstract: An intake manifold is connected to a cylinder of an engine, and extends backward from the cylinder. A throttle body is attached to the intake manifold. As seen in a plan view of an outboard motor, the throttle body is disposed backward of a head cover, while being disposed inward of a lateral end of the intake manifold in a right-and-left direction of the outboard motor.Type: ApplicationFiled: September 23, 2019Publication date: June 25, 2020Inventors: Shinya MAEKAWA, Makoto MORINO, Koichi NAKAYAMA
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Patent number: 10618620Abstract: An outboard motor includes an engine including a crankshaft, a generator including a rotor that rotates together with the rotation of the crankshaft and a stator in which a coil is wound so as to face the rotor, and a fan including a blade disposed coaxially with the rotor, provided separately from the rotor, and that rotates together with the rotation of the rotor.Type: GrantFiled: July 3, 2018Date of Patent: April 14, 2020Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Takahiro Matsui, Makoto Morino
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Publication number: 20200066726Abstract: A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: Fredrick D. Fishburn, Haitao Liu, Soichi Sugiura, Oscar O. Enomoto, Mark A. Zaleski, Keisuke Hirofuji, Makoto Morino, Ichiro Abe, Yoshiyuki Nanjo, Atsuko Otsuka
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Patent number: 10464646Abstract: In an outboard motor, one of an engine control unit and a power supply control unit is mounted on a first side surface of an engine, and the other of the engine control unit and the power supply control unit is mounted on an upper surface of the engine.Type: GrantFiled: January 5, 2018Date of Patent: November 5, 2019Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Yoshihiro Mizushima, Takeshi Naito, Makoto Morino
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Publication number: 20190031310Abstract: An outboard motor includes an engine including a crankshaft, a generator including a rotor that rotates together with the rotation of the crankshaft and a stator in which a coil is wound so as to face the rotor, and a fan including a blade disposed coaxially with the rotor, provided separately from the rotor, and that rotates together with the rotation of the rotor.Type: ApplicationFiled: July 3, 2018Publication date: January 31, 2019Inventors: Takahiro MATSUI, Makoto MORINO
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Publication number: 20180222562Abstract: In an outboard motor, one of an engine control unit and a power supply control unit is mounted on a first side surface of an engine, and the other of the engine control unit and the power supply control unit is mounted on an upper surface of the engine.Type: ApplicationFiled: January 5, 2018Publication date: August 9, 2018Inventors: Yoshihiro MIZUSHIMA, Takeshi NAITO, Makoto MORINO
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Patent number: 7499340Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: GrantFiled: January 9, 2008Date of Patent: March 3, 2009Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20080205111Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: ApplicationFiled: January 9, 2008Publication date: August 28, 2008Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7345929Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: GrantFiled: March 7, 2007Date of Patent: March 18, 2008Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20070242535Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.Type: ApplicationFiled: March 7, 2007Publication date: October 18, 2007Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7203101Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: January 12, 2006Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Publication number: 20060120125Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: ApplicationFiled: January 12, 2006Publication date: June 8, 2006Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7016236Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: April 8, 2005Date of Patent: March 21, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6954386Abstract: A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.Type: GrantFiled: February 20, 2003Date of Patent: October 11, 2005Assignees: Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.Inventors: Seiji Narui, Kenji Mae, Makoto Morino, Shuichi Kubouchi
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Publication number: 20050179058Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: ApplicationFiled: April 8, 2005Publication date: August 18, 2005Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 6915476Abstract: A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.Type: GrantFiled: December 7, 2004Date of Patent: July 5, 2005Assignees: Elpida Memory, Inc., Hitachi ULSI Systems Co. Ltd., Hitachi, Ltd.Inventors: Makoto Morino, Masayuki Nakamura
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Publication number: 20050122800Abstract: A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.Type: ApplicationFiled: December 7, 2004Publication date: June 9, 2005Inventors: Makoto Morino, Masayuki Nakamura
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Patent number: 6898130Abstract: A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.Type: GrantFiled: October 14, 2003Date of Patent: May 24, 2005Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata