Patents by Inventor Makoto Murai

Makoto Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200062031
    Abstract: An omnidirectional wheel includes a plurality of first and second rollers, a plurality of roller support parts, a wheel hub, and a fixing member. The wheel hub has a shaft portion and an extension. The fixing member and an elastic body are disposed to surround the shaft portion. Spaces are provided between the elastic body and the shaft portion, or between the elastic body and the roller support parts. A plurality of first pins and second pins are formed to protrude from the extension and the fixing member, respectively. The elastic body has a plurality of first holes and second holes. The first holes and the second holes are shifted from each other in a circumferential direction of the elastic body.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 27, 2020
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventor: Makoto MURAI
  • Publication number: 20190377353
    Abstract: An autonomous cart includes an obstacle detecting member, a driving member, a storing section, and a control section. The obstacle detecting member outputs detection information including an obstacle position and obstacle luminance within a planar obstacle-detection region. The storing section stores designated area map information indicating a position of an obstacle within a designated area. At least one command member to which a command for the control section is assigned is included in the obstacle and is disposed within the designated area at a position where execution of the command is desired. The control section controls the driving member based on the designated area map information and a current position of the autonomous cart to cause the autonomous cart to autonomously travel while avoiding the obstacle within the designated area. The control section follows the command detected by the control section based on the obstacle luminance in the detection information.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 12, 2019
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventor: Makoto MURAI
  • Patent number: 10418340
    Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 17, 2019
    Assignee: SONY CORPORATION
    Inventors: Makoto Murai, Yuji Takaoka, Kazuki Sato, Hiroyuki Yamada
  • Patent number: 10300475
    Abstract: A circumferential coating material which is coated on a circumferential surface of a honeycomb structure monolithically formed by extrusion, to form a circumferential coating layer, the circumferential coating material containing fused silica in a range of 20 to 75 mass %, containing a color developing agent in a range of 5 to 50 mass %, containing colloidal silica in a range of 5 to 30 mass %, and further containing a silicon based water repellent agent in a range of 1 to 10 mass % to a total mass of the fused silica, the color developing agent, and the colloidal silica.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 28, 2019
    Assignee: NGK Insulators, Ltd.
    Inventors: Shuji Ueda, Shungo Nagai, Takayoshi Shibayama, Yoshihiro Sato, Makoto Murai, Kojiro Hayashi
  • Publication number: 20190013419
    Abstract: [Object] To reduce the size of a semiconductor device having a semiconductor chip mounted thereon while reducing the influence of thermal conduction to the semiconductor chip in the semiconductor device. [Solution] In the semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.
    Type: Application
    Filed: November 30, 2016
    Publication date: January 10, 2019
    Inventor: MAKOTO MURAI
  • Patent number: 10093808
    Abstract: A circumferential coating material contains colloidal silica, silicon carbide, and titanium oxide different in particle diameters from silicon carbide, coats a circumferential surface of a honeycomb structure monolithically formed by extrusion, including as a main component, cordierite having a porosity of 50 to 75%, and forms a circumferential coating layer. A circumferentially coated honeycomb structure has a honeycomb structure comprising latticed porous partition walls defining and forming a plurality of polygonal cells forming through channels and extending from one end face to the other end face, and a circumferential coating layer formed by coating at least a part of a circumferential surface of the honeycomb structure with the circumferential coating material.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: October 9, 2018
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Murai, Yoshihiro Sato, Kazunari Akita
  • Patent number: 10014248
    Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 3, 2018
    Assignee: SONY CORPORATION
    Inventors: Makoto Murai, Yuji Takaoka, Hiroyuki Yamada, Kazuki Sato, Makoto Imai
  • Publication number: 20180178206
    Abstract: A circumferential coating material which is coated on a circumferential surface of a honeycomb structure monolithically formed by extrusion, to form a circumferential coating layer, the circumferential coating material containing fused silica in a range of 20 to 75 mass %, containing a color developing agent in a range of 5 to 50 mass %, containing colloidal silica in a range of 5 to 30 mass %, and further containing a silicon based water repellent agent in a range of 1 to 10 mass % to a total mass of the fused silica, the color developing agent, and the colloidal silica.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 28, 2018
    Applicant: NGK INSULATORS, LTD.
    Inventors: Shuji Ueda, Shungo Nagai, Takayoshi Shibayama, Yoshihiro Sato, Makoto Murai, Kojiro Hayashi
  • Patent number: 9918970
    Abstract: Disclosed is a pharmaceutical composition comprising a complex between solifenacin or a pharmaceutically acceptable salt thereof and an ion exchange resin, and an acrylic based polymer.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: March 20, 2018
    Assignee: Astellas Pharma Inc.
    Inventors: Tatsunobu Yoshioka, Makoto Murai, Hiroaki Tasaki
  • Patent number: 9676912
    Abstract: To provide a technique related to a marking base that allows clear marking by ink and is excellent in thermal resistance and chemical resistance. A marking base composition contains inorganic particles of 27 to 50 mass %, an inorganic binder of 5 to 20 mass %, an organic binder of 3 to 16 mass %, a thermal expansion resin of 1 to 3 mass %, and an organic solvent.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 13, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Murai, Akifumi Nishio, Yasumasa Fujioka, Masanari Iwade
  • Publication number: 20170162493
    Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.
    Type: Application
    Filed: June 5, 2015
    Publication date: June 8, 2017
    Inventors: MAKOTO MURAI, YUJI TAKAOKA, HIROYUKI YAMADA, KAZUKI SATO, MAKOTO IMAI
  • Publication number: 20170148760
    Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 25, 2017
    Inventors: MAKOTO MURAI, KAZUKI SATO, HIROYUKI YAMADA, YUJI TAKAOKA, MAKOTO IMAI, SHIGEKI AMANO
  • Publication number: 20170141065
    Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 18, 2017
    Inventors: MAKOTO MURAI, YUJI TAKAOKA, KAZUKI SATO, HIROYUKI YAMADA
  • Publication number: 20170141064
    Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 18, 2017
    Inventors: MAKOTO MURAI, YUJI TAKAOKA
  • Publication number: 20170002205
    Abstract: A circumferential coating material contains colloidal silica, silicon carbide, and titanium oxide different in particle diameters from silicon carbide, coats a circumferential surface of a honeycomb structure monolithically formed by extrusion, including as a main component, cordierite having a porosity of 50 to 75%, and forms a circumferential coating layer. A circumferentially coated honeycomb structure has a honeycomb structure comprising latticed porous partition walls defining and forming a plurality of polygonal cells forming through channels and extending from one end face to the other end face, and a circumferential coating layer formed by coating at least a part of a circumferential surface of the honeycomb structure with the circumferential coating material.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Applicant: NGK INSULATORS, LTD.
    Inventors: Makoto MURAI, Yoshihiro SATO, Kazunari AKITA
  • Patent number: 9425070
    Abstract: Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 23, 2016
    Assignee: SONY CORPORATION
    Inventors: Yoshimichi Harada, Makoto Murai, Takayuki Tanaka, Kana Nagayoshi, Takuya Nakamura
  • Patent number: 9368480
    Abstract: Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: June 14, 2016
    Assignee: SONY CORPORATION
    Inventor: Makoto Murai
  • Publication number: 20150179614
    Abstract: Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.
    Type: Application
    Filed: November 21, 2014
    Publication date: June 25, 2015
    Inventor: Makoto Murai
  • Patent number: 9041199
    Abstract: A semiconductor device includes: a mount body; a semiconductor chip mounted on the mount body via projecting connecting terminals; and a filling resin filled between the mount body and the semiconductor chip to seal the connecting terminals, the filling resin being retained inside the semiconductor chip in such a way as not to run out of at least one side portion in four side portions defining an outer peripheral portion of the semiconductor chip.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: May 26, 2015
    Assignee: Sony Corporation
    Inventors: Makoto Murai, Yoshimichi Harada
  • Publication number: 20150024190
    Abstract: To provide a technique related to a marking base that allows clear marking by ink and is excellent in thermal resistance and chemical resistance. A marking base composition contains inorganic particles of 27 to 50 mass %, an inorganic binder of 5 to 20 mass %, an organic binder of 3 to 16 mass %, a thermal expansion resin of 1 to 3 mass %, and an organic solvent.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventors: Makoto MURAI, Akifumi NISHIO, Yasumasa FUJIOKA, Masanari IWADE