Patents by Inventor Makoto Nakanishi

Makoto Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040078412
    Abstract: A method for solving an eigenvalue problem is divided into three steps of tri-diagonalizing a matrix; calculating an eigenvalue and an eigenvector based on the tri-diagonal matrix; and converting the eigenvector calculated based on the tri-diagonal matrix and calculating the eigenvector of the original matrix. In particular, since the cost of performing the tri-diagonalization step and original matrix eigenvector calculation step are large, these steps can be processed in parallel and the eigenvalue problem can be solved at high speed.
    Type: Application
    Filed: October 2, 2003
    Publication date: April 22, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Makoto Nakanishi
  • Publication number: 20040075075
    Abstract: The present invention provides a Y-type hexagonal ferrite thin film suitable for high frequency devices, having a crystal structure with the c-axis oriented perpendicular to the surface of the thin film. The present invention also provides a method of producing the Y-type hexagonal ferrite thin film, comprising the steps of preparing a viscous solution containing a metal-organic complex which is formed using a primary component including a Fe+3 ion, and a secondary component including a Ba2+ ion, at least one transition metal ion selected from the group consisting of Fe2+, Co2+, Ni2+, Zn2+, CU2+ and Mn2+; and optionally at least one metal ion selected from the group consisting of Sr2+, Ca2+ and Pb2+, forming a film having a Y-type ferrite composition on a surface made of noble metal through a coating process using the viscous solution, and burning the film at a temperature of 750° C. or more.
    Type: Application
    Filed: November 4, 2003
    Publication date: April 22, 2004
    Inventors: Jun Takada, Tatsuo Fujii, Makoto Nakanishi
  • Patent number: 6710464
    Abstract: A sealing material in a plate form is placed on a frame wherein a recess is provided. A semiconductor chip and the frame are overlapped via the sealing material in a plate form within a thermostatic chamber of which the temperature is higher than the temperature at the time of the sealing of the semiconductor chip and the frame in a resin. After that, the semiconductor chip and the frame, which overlap each other, are taken out of the thermostatic chamber so as to be cooled down in the atmosphere. After that, they are sealed in a molding resin. The semiconductor chip is secured to the frame due to the differential pressure (negative pressure) between the pressure within the airtight space and atmospheric pressure. Thereby, a resin mold semiconductor device is gained wherein a semiconductor chip is secured to a frame without using a die bonding material.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: March 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Yamaguchi, Makoto Nakanishi
  • Publication number: 20040048151
    Abstract: A positive electrode plate (7) and a negative electrode plate (8) are coiled around with a separator (9) interposed therebetween into a flat shape having a rectangular plan to obtain an intermediate product (17) of an electrode plate group, whose corners are then cut off along straight or curved lines to obtain a substantially octagonal electrode plate group (1a, 1b), so that it is accommodated in a negative electrode case (5) having a circular plan with good space efficiency. The problem of residual water in the coiled electrode plate group (1a, 1b, 1c) of a coin type battery having high load current characteristics is resolved by a vacuum dry treatment, and the problem of dust generated during the welding of leads is resolved by a method whereby dust is not scattered inside the case. Flat batteries with higher reliability are thus obtained.
    Type: Application
    Filed: April 4, 2003
    Publication date: March 11, 2004
    Inventors: Tetsuya Hayashi, Makoto Nakanishi
  • Publication number: 20040007160
    Abstract: A method of manufacturing aluminum-substituted hematite represented by &agr;-(Fe1−xAlx)2O3 where x=0.01 to 0.15, by mixing an iron compound and an aluminum compound such that an atomic ratio of Fe to Al falls within the range of 99:1 to 85:15, adding citric acid and ethylene glycol to the mixture of the iron compound and aluminum compound to produce a gel, and pyrolyzing the gel, followed by calcining the pyrolyzed product.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 15, 2004
    Inventors: Jun Takada, Tatsuo Fujii, Makoto Nakanishi
  • Publication number: 20030187898
    Abstract: A method for solving an eigenvalue problem is divided into three steps of tri-diagonalizing a matrix; calculating an eigenvalue and an eigenvector based on the tri-diagonal matrix; and converting the eigenvector calculated based on the tri-diagonal matrix and calculating the eigenvector of the original matrix. In particular, since the cost of performing the tri-diagonalization step and original matrix eigenvector calculation step are large, these steps can be processed in parallel and the eigenvalue problem can be solved at high speed.
    Type: Application
    Filed: November 7, 2002
    Publication date: October 2, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Makoto Nakanishi
  • Publication number: 20030182518
    Abstract: An LU decomposition is carried out on a block E and H. Then, a block B is updated using an upper triangular portion of the block E, and a block D is updated using a lower triangular portion of the block E. At this time, in an LU decomposition, blocks F and I have been updated. Then, using the blocks B, D, F, and H, blocks A, C, G, and I are updated, an upper triangular portion of the block E is updated, and finally, the blocks D and F are updated. Then, the second updating process is performed on the block E. Using the result of the process, the blocks B and H are updated. Finally, the block E is updated, and the pivot interchanging process is completed, thereby terminating the process. These processes on the blocks are performed in a plurality of divided threads in parallel.
    Type: Application
    Filed: November 6, 2002
    Publication date: September 25, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Makoto Nakanishi
  • Publication number: 20030175817
    Abstract: A novel action mechanism wherein androgen receptor (AR) is activated by the interaction between cyclin E and the androgen receptor was revealed. This activation is resistant to existing anti-androgen agents and both androgen receptor ligand-dependent and independent activations were found to participate in this mechanism. Methods of screening for anti-androgen agents using cyclin E are also provided by the present invention. Based on the findings as described above, novel anti-androgen agents can be screened. These anti-androgen agents are expected to be efficacious also against pathological conditions that have become resistant to existing anti-androgen agents. Thus, the instant invention opens up new possibilities for treatment using anti-androgen agents that had their limitations until now.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 18, 2003
    Inventors: Kyoji Ikeda, Makoto Nakanishi, Shigeaki Kato
  • Publication number: 20030162088
    Abstract: A coin type battery having a structure that contributes to improved discharge capacity and prevent deposition of lithium metal is provided. A positive electrode plate (7) and a negative electrode plate (8) are folded at their connecting pieces and coiled around into a flat shape to construct an electrode plate group (1) such that layer faces of the positive electrode plate (7) and layer faces of the negative electrode plate (8) are alternately layered upon one another with a separator (9) interposed therebetween, and the electrode plate group is accommodated in a battery case made of a cap case (4) having an open end and a sealing case (5) for sealing this open end. An insulating member is provided to a connecting piece of the positive electrode plate (7) that is to be located at the center when the electrode plates are coiled around, on a face opposite one end of the negative electrode plate (8).
    Type: Application
    Filed: March 11, 2003
    Publication date: August 28, 2003
    Inventors: Makoto Nakanishi, Koshi Takamura, Hiroyuki Akiya, Nobuharu Koshiba
  • Publication number: 20030047815
    Abstract: A sealing material in a plate form is placed on a frame wherein a recess is provided. A semiconductor chip and the frame are overlapped via the sealing material in a plate form within a thermostatic chamber of which the temperature is higher than the temperature at the time of the sealing of the semiconductor chip and the frame in a resin. After that, the semiconductor chip and the frame, which overlap each other, are taken out of the thermostatic chamber so as to be cooled down in the atmosphere. After that, they are sealed in a molding resin. The semiconductor chip is secured to the frame due to the differential pressure (negative pressure) between the pressure within the airtight space and atmospheric pressure. Thereby, a resin mold semiconductor device is gained wherein a semiconductor chip is secured to a frame without using a die bonding material.
    Type: Application
    Filed: July 8, 2002
    Publication date: March 13, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Makoto Nakanishi
  • Publication number: 20020182494
    Abstract: A power generation element is stored in an inner space formed by combining a battery case (2) and a seal case (3) formed as a half-shell body with a rectangular plane shape such that the individual openings are placed opposing to each other with a gasket (4) interposed therebetween, and the gasket (4) is pressed between the open end of the battery case (2) and a step (35) of the seal case (3) for sealing during caulking. Because recesses (36) are formed on the individual peripheral edges of a bottom surface (31) of the seal case (3), the strength of straight parts of a seal-case side-peripheral surface (32) of the seal case (3) increases against a seal pressure during caulking, and a decrease of seal capability caused by the straight parts bulging toward the outside during sealing is prevented.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 5, 2002
    Inventors: Tetsuya Hayashi, Makoto Nakanishi, Kunihiko Bessho
  • Publication number: 20020143658
    Abstract: An information providing unit of a server reads a menu table in accordance with a request sent from a customer terminal. The customer terminal presents menu items together with their nutritive values to a customer in accordance with data sent from the server. A selection process unit of the server specifies a dish to be ordered from a cooking service provider in accordance with an instruction sent from the customer terminal. An order process unit of the server searches a cooking material database in order to specify a cooking material necessary for making the dish. A monetary matter process unit of the server performs a process for collecting a charge for the provided service from the cooking service provider or from a cooking material provider.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 3, 2002
    Inventors: Kenji Kuwana, Yukiko Inada, Takahisa Hanajima, Makoto Nakanishi, Fumikazu Wakaki, Yumi Watanabe
  • Publication number: 20020099748
    Abstract: In a preconditioning process for an iteration method to solve simultaneous linear equations through multilevel block incomplete factorization of a coefficient matrix, a set of variable numbers of variables to be removed is determined at each level of the factorization such that a block matrix comprising coefficients of the variables can be diagonal dominant. The approximate inverse matrix of the block matrix is obtained in iterative computation, and non-zero elements of a coefficient matrix at a coarse level are reduced.
    Type: Application
    Filed: June 26, 2001
    Publication date: July 25, 2002
    Inventors: Lutz Grosz, Makoto Nakanishi
  • Publication number: 20020090752
    Abstract: A low-cost semiconductor device, and an apparatus and a method for die bonding such a semiconductor device using no or extremely small quantities of bonding materials containing Pb, as well as other bonding materials, from the consideration to the environment. In a semiconductor device including a die 1 and a die pad 2 fixed to each other at facing surfaces 1a and 2a, a hollow portion 3 is formed in at least a part of the facing surfaces 1a and 2a, and the die 1 and the die pad 2 are fixed so that the internal pressure of the hollow portion 3 is kept lower than the external pressure.
    Type: Application
    Filed: July 20, 2001
    Publication date: July 11, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Makoto Nakanishi
  • Publication number: 20020091909
    Abstract: In accordance with a parallel matrix processing method adopted in a shared-memory scalar computer, a matrix to be subjected to LU factorization is divided into a block D of the diagonal portion and blocks beneath the D diagonal block such as L1, L2 and L3. Then, D+L1, D+L2 and D+L3 are assigned to 3 processors respectively for processing them in parallel. Next, a block U is updated by adopting an LU-factorization method and C1 to C3 are updated with L1 to L3 and U. By carrying out this processing on the inner side gradually decreasing in size as blocks, finally, a portion corresponding to the D diagonal block remains to be processed. By applying the LU factorization to this D portion, the LU factorization for the entire matrix can be completed.
    Type: Application
    Filed: March 20, 2001
    Publication date: July 11, 2002
    Inventor: Makoto Nakanishi
  • Publication number: 20020065862
    Abstract: Three-dimensional data that is processed is divided by the number of threads in the third dimensional direction and stored to respective secondary cache memories of the threads. Each thread Fourier transforms data stored in the secondary cache in the first dimensional direction and the second dimensional direction. As a result, a two-dimensional Fourier transform can be performed in parallel at a time. The resultant data that has been two-dimensionally transformed is restored to a shared memory. Each thread Fourier transforms the data in the third dimensional direction.
    Type: Application
    Filed: March 21, 2001
    Publication date: May 30, 2002
    Inventor: Makoto Nakanishi
  • Publication number: 20020012964
    Abstract: In a quest for human Cds1 (hCds1) homologous to yeast cell cycle regulating factors fission yeast spCds1 and budding yeast scCds1, GenBank EST database was searched based on spCds1 sequence and scCds1 sequence to find a Drosophila homologue having a significant homology to spCds1 and scCds1. Using these sequences, the full-length gene of hCds1 was isolated. The gene was strongly expressed in the testis and was widely expressed in other tissues as well. Furthermore, the protein encoded by the isolated gene was prepared as a recombinant protein, and the kinase activity thereof was detected in vitro, to find that the protein efficiently phosphorylated cdc25 and histone H1.
    Type: Application
    Filed: December 19, 2000
    Publication date: January 31, 2002
    Inventor: Makoto Nakanishi
  • Patent number: 5887186
    Abstract: A simultaneous linear equations calculation method using a memory-distributed parallel processor and the memory-distributed parallel processor solves simultaneous linear equations in an LU decomposition method in block units using an outer product. According to the method and the processor, data of column vector blocks is rearranged through a cyclic and parallel rearrangement and transfer. When an LU decomposition is performed, data to be processed in a row matrix product is divided, and the divided data is processed in a matrix calculation and simultaneously transferred for a subsequent matrix product calculation. The LU-decomposed matrix is restored to an original arrangement and then rearranged such that the matrix is divided in the row vector direction to realize a forward/backward substitution process in parallel in each processor.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: March 23, 1999
    Assignee: Fujitsu Limited
    Inventor: Makoto Nakanishi
  • Patent number: 5786641
    Abstract: A failure detection system detects a failure in a by-pass switch of a power converter. The by-pass switch switches the electric power supply so that electric power is supplied from a standby power source to a load instead of from a power converter. A switch operation circuit turns the by-pass switch on and off. A first current detector detects the inverted output current of the power converter. A second current detector detects the load current flowing through the load. An operational amplifier adds the outputs of the first and second current detectors. A comparator detects a failure of the by-pass switch. If the addition result given by the operational amplifier is outside a predetermined range of values when the switch operation circuit is turned off, the comparator concludes that the by-pass switch has a failure.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: July 28, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Makoto Nakanishi, Katsumi Ikeda
  • Patent number: 5751616
    Abstract: Two-dimensional real number data are stored in a two-dimensional array spanning plural processors. Each subarray in each processor is divided into two sets of row vectors and one set is referred to as a real part while the other set is referred to as an imaginary part. A result of a real Fourier transformation with respect to columns performed on each row vector is obtained after performing a complex Fourier transformation in each processor. Then, the two-dimensional array is transposed by transferring data in parallel to perform a complex Fourier transformation with respect to rows, the result of which is transposed again to obtain a result of a two-dimensional Fourier transformation. The Fourier transformations can be performed in the closed state in each processor, thereby greatly improving an efficiency of the entire process.
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: May 12, 1998
    Assignees: Fujitsu Limited, The Australian National University
    Inventors: Markus Hegland, Makoto Nakanishi