Patents by Inventor Makoto Orikasa

Makoto Orikasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784122
    Abstract: A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base material includes: a step of forming a trench including a bottom surface to which a foundation layer is exposed, and a lateral surface which includes a surface of a trench formation layer, according to an imprint method; and a step of forming an electroconductive pattern layer by growing metal plating from the foundation layer which is exposed to the bottom surface of the trench.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 22, 2020
    Assignee: TDK CORPORATION
    Inventors: Takashi Daitoku, Susumu Taniguchi, Akiko Seki, Atsushi Sato, Yuhei Horikawa, Makoto Orikasa, Hisayuki Abe
  • Publication number: 20200211951
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: TDK CORPORATION
    Inventors: Takashi DAITOKU, Susumu TANIGUCHI, Akiko SEKI, Atsushi SATO, Yuhei HORIKAWA, Makoto ORIKASA, Hisayuki ABE
  • Patent number: 10374301
    Abstract: Disclosed herein is a wiring component that includes a base material and a planar coil pattern formed on the base material. The planar coil pattern includes a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion connected to the first connecting position; and a connection wiring portion that short-circuits the second connecting position and the third connecting position. A cross-section structure of the planar coil pattern has a base resin layer formed on the base material, and a conductive layer formed on the base resin layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 6, 2019
    Assignee: TDK CORPORATION
    Inventors: Yuhei Horikawa, Makoto Orikasa, Yoshihiro Kanbayashi, Hisayuki Abe, Hirohumi Asou, Kosuke Kunitsuka
  • Patent number: 10354796
    Abstract: Disclosed herein is a method for manufacturing a planar coil, the method including forming a base conductive layer on a base material, the base conductive layer including: a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion that connects the first connecting position with an external power source; and a connection wiring portion that short-circuits the second connecting position and the third connecting position; forming a wiring conductive layer on the base conductive layer by electrolytic plating by feeding power from the external power source; and removing the power-feed wiring portion and the connection wiring portion.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Yuhei Horikawa, Makoto Orikasa, Yoshihiro Kanbayashi, Hisayuki Abe, Hirohumi Asou, Kosuke Kunitsuka
  • Patent number: 10354973
    Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 10304779
    Abstract: Disclosed herein is an electronic component module that includes, an electronic component, a mold resin that seals the electronic component, a conductive film that covers the mold resin, and a protective film that covers the conductive film. The protective film includes a protective layer and a low reflective layer, and the low reflective layer is free from contacting the conductive film.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 28, 2019
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Yuhei Horikawa, Hisayuki Abe, Yoshihiro Kanbayashi
  • Publication number: 20190043736
    Abstract: A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base material includes: a step of forming a trench including a bottom surface to which a foundation layer is exposed, and a lateral surface which includes a surface of a trench formation layer, according to an imprint method; and a step of forming an electroconductive pattern layer by growing metal plating from the foundation layer which is exposed to the bottom surface of the trench.
    Type: Application
    Filed: July 18, 2018
    Publication date: February 7, 2019
    Applicant: TDK CORPORATION
    Inventors: Takashi DAITOKU, Susumu TANIGUCHI, Akiko SEKI, Atsushi SATO, Yuhei HORIKAWA, Makoto ORIKASA, Hisayuki ABE
  • Publication number: 20190032221
    Abstract: A sheet material includes a resin layer containing a binder and polypyrrole particles, an electroless plating film provided on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a transparent base material provided on the side of the other main surface of the resin layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 31, 2019
    Applicants: TDK CORPORATION, ACHILLES CORPORATION
    Inventors: Makoto ORIKASA, Yuhei HORIKAWA, Yoshihiro KANBAYASHI, Hisayuki ABE, Hiroki ASHIZAWA, Miho MORI, Misaki TAMURA
  • Publication number: 20190032219
    Abstract: A sheet material includes a resin layer containing a binder and catalyst particles, an electroless plating film on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a base material on the side of the other main surface of the resin layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 31, 2019
    Applicant: TDK CORPORATION
    Inventors: Makoto ORIKASA, Yuhei HORIKAWA, Yoshihiro KANBAYASHI, Hisayuki ABE
  • Publication number: 20190035719
    Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 31, 2019
    Applicant: TDK CORPORATION
    Inventors: Takashi DAITOKU, Susumu TANIGUCHI, Akiko SEKI, Atsushi SATO, Yuhei HORIKAWA, Makoto ORIKASA, Hisayuki ABE
  • Publication number: 20190013293
    Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 10, 2019
    Applicant: TDK CORPORATION
    Inventors: Makoto ORIKASA, Hideyuki SEIKE, Yuhei HORIKAWA, Hisayuki ABE
  • Patent number: 10163847
    Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 25, 2018
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Publication number: 20180254255
    Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
    Type: Application
    Filed: March 3, 2017
    Publication date: September 6, 2018
    Applicant: TDK CORPORATION
    Inventors: Makoto ORIKASA, Hideyuki SEIKE, Yuhei HORIKAWA, Hisayuki ABE
  • Publication number: 20180174748
    Abstract: Disclosed herein is a method for manufacturing a planar coil, the method including forming a base conductive layer on a base material, the base conductive layer including: a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion that connects the first connecting position with an external power source; and a connection wiring portion that short-circuits the second connecting position and the third connecting position; forming a wiring conductive layer on the base conductive layer by electrolytic plating by feeding power from the external power source; and removing the power-feed wiring portion and the connection wiring portion.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 21, 2018
    Applicant: TDK Corporation
    Inventors: Yuhei Horikawa, Makoto Orikasa, Yoshihiro Kanbayashi, Hisayuki Abe, Hirohumi Asou, Kosuke Kunitsuka
  • Publication number: 20180175494
    Abstract: Disclosed herein is a wiring component that includes a base material and a planar coil pattern formed on the base material. The planar coil pattern includes a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion connected to the first connecting position; and a connection wiring portion that short-circuits the second connecting position and the third connecting position. A cross-section structure of the planar coil pattern has a base resin layer formed on the base material, and a conductive layer formed on the base resin layer.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 21, 2018
    Applicant: TDK Corporation
    Inventors: Yuhei Horikawa, Makoto Orikasa, Yoshihiro Kanbayashi, Hisayuki Abe, Hirohumi Asou, Kosuke Kunitsuka
  • Publication number: 20180114759
    Abstract: Disclosed herein is an electronic component module that includes, an electronic component, a mold resin that seals the electronic component, a conductive film that covers the mold resin, and a protective film that covers the conductive film. The protective film includes a protective layer and a low reflective layer, and the low reflective layer is free from contacting the conductive film.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 26, 2018
    Applicant: TDK Corporation
    Inventors: Makoto ORIKASA, Yuhei HORIKAWA, Hisayuki ABE, Yoshihiro KANBAYASHI
  • Patent number: 9818736
    Abstract: A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: November 14, 2017
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 9640500
    Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: May 2, 2017
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 9620156
    Abstract: A magnetic head device with high joint strength in an arm and a suspension is provided. The magnetic head device comprises an arm, a suspension overlapping with a leading end part of the arm, a slider located at a leading end part of the suspension, and a joint part that is located between the leading end part of the arm and the suspension and that joins the arm and the suspension, while the joint part includes Sn.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 11, 2017
    Assignee: TDK CORPORATION
    Inventors: Katsuhiko Igarashi, Makoto Orikasa, Takashi Kawashima, Hisayuki Abe
  • Patent number: 9514772
    Abstract: A magnetic head device which has strong joint strength in an arm and a suspension and high accuracy of a size and a shape is provided. The magnetic head device comprises an arm, a suspension overlapping with a leading end part of the arm, a slider located at a leading end part of the suspension, and a first joint part that is placed between the leading end part of the arm and the suspension and that joins the arm and the suspension, the first joint part including Sn or a resin adhesive.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: December 6, 2016
    Assignee: TDK CORPORATION
    Inventors: Takashi Kawashima, Toru Mizuno, Katsuhiko Igarashi, Makoto Orikasa, Hidetoshi Suzuki