Abstract: In a data processor including a master circuit that issues an access request and slave circuits that perform processing in response to the access request received from the master circuit, the disclosed invention enables the master circuit to access all data areas of the slave circuits even if the master circuit does not have an access command in data size suitable for accessing the slave circuit. An access size control unit that can convert access size input from the master circuit to data size in which the slave circuit accepts access is installed between the master circuit and the slave circuit. The access size control unit retains at least one address for access size setting. As the master circuit accesses the appropriate address for access size setting, the access size conversion procedure can be carried out.

Abstract: In the address translation, there is a region in which the translation having a common regularity is possible into a plurality of regions, and a region in which such a translation is not possible. An address translation circuit is disposed between a master circuit and a slave circuit. The address translation to the former region is performed by a translation system in which the translated address is produced by a manipulation including permutation of a part of the original address, and the address translation to the latter region is performed by an address translation system in which a part of the original address is replaced with translated address information stored beforehand. The data processor includes the address translation circuit having both of the translation systems.