Patents by Inventor Makoto Yabuuchi
Makoto Yabuuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8659969Abstract: By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.Type: GrantFiled: August 22, 2011Date of Patent: February 25, 2014Assignee: Renesas Electronics CorporationInventors: Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, Kazutami Arimoto
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Publication number: 20140016391Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: September 13, 2013Publication date: January 16, 2014Applicant: Renesas Electronics CorporationInventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA
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Patent number: 8547723Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: February 16, 2012Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20130077387Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.Type: ApplicationFiled: September 12, 2012Publication date: March 28, 2013Inventor: Makoto YABUUCHI
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Patent number: 8310883Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: GrantFiled: July 28, 2011Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Koji Nii
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Publication number: 20120224405Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: February 16, 2012Publication date: September 6, 2012Inventors: Shinji TANAKA, Makoto Yabuuchi, Yuta Yoshida
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SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION
Publication number: 20120087198Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: ApplicationFiled: December 14, 2011Publication date: April 12, 2012Applicant: Renesas Electronics CorporationInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Publication number: 20120044777Abstract: By using a fact that a bit error in an on-chip embedded memory occurs at a random address, means for creating a chip-unique ID and utilizing this ID are provided. A controller having received a verification request from outside instructs a variable power supply circuit to decrease a voltage supplied to a memory to be lower than that at the normal operation time. When the voltage supplied to the memory is stabilized, the controller requests a memory test to a memory BIST. By using an address where an error occurs due to a result of the memory test, the controller creates the chip-unique ID and uses the ID as a response to the verification request.Type: ApplicationFiled: August 22, 2011Publication date: February 23, 2012Inventors: Hidehiro FUJIWARA, Koji NII, Makoto Yabuuchi, Kazutami Arimoto
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Semiconductor memory device with adjustable selected word line potential under low voltage condition
Patent number: 8098533Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: GrantFiled: June 25, 2009Date of Patent: January 17, 2012Assignee: Renesas Electronics CorporationInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Publication number: 20110286291Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: ApplicationFiled: July 28, 2011Publication date: November 24, 2011Applicant: Renesas Electronics CorporationInventors: Makoto YABUUCHI, Koji NII
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Patent number: 8018785Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: GrantFiled: October 21, 2010Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Koji Nii
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Publication number: 20110032750Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: ApplicationFiled: October 21, 2010Publication date: February 10, 2011Applicant: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Koji Nii
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Patent number: 7876625Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: GrantFiled: September 8, 2009Date of Patent: January 25, 2011Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Koji Nii
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Publication number: 20090323398Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: ApplicationFiled: September 8, 2009Publication date: December 31, 2009Applicant: RENESAS TECHNOLOGY CORPInventors: Makoto Yabuuchi, Koji Nii
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Semiconductor memory device with adjustable selected work line potential under low voltage condition
Publication number: 20090268531Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: ApplicationFiled: June 25, 2009Publication date: October 29, 2009Applicant: Renesas Technology Corp.Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Patent number: 7602654Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: GrantFiled: August 9, 2007Date of Patent: October 13, 2009Assignee: Renesas Technology CorporationInventors: Makoto Yabuuchi, Koji Nii
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Semiconductor memory device with adjustable selected work line potential under low voltage condition
Patent number: 7570525Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: GrantFiled: July 25, 2006Date of Patent: August 4, 2009Assignee: Renesas Technology Corp.Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi -
Publication number: 20080037358Abstract: A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Inventors: Makoto Yabuuchi, Koji Nii
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Publication number: 20070030741Abstract: A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.Type: ApplicationFiled: July 25, 2006Publication date: February 8, 2007Applicant: Renesas Technology Corp.Inventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi