Patents by Inventor Makoto Yabuuchi
Makoto Yabuuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9721648Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.Type: GrantFiled: July 19, 2016Date of Patent: August 1, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Yabuuchi
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Patent number: 9697886Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.Type: GrantFiled: July 15, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Shinji Tanaka
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Patent number: 9697911Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.Type: GrantFiled: October 28, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventor: Makoto Yabuuchi
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Patent number: 9685205Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.Type: GrantFiled: July 15, 2016Date of Patent: June 20, 2017Assignee: Renesas Electronics CorporationInventor: Makoto Yabuuchi
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Patent number: 9672900Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.Type: GrantFiled: February 24, 2016Date of Patent: June 6, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Nii, Shigeki Ohbayashi, Yasumasa Tsukamoto, Makoto Yabuuchi
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Publication number: 20170092352Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: ApplicationFiled: December 9, 2016Publication date: March 30, 2017Inventors: Toshiaki SANO, Ken SHIBATA, Shinji TANAKA, Makoto YABUUCHI, Noriaki MAEDA
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Publication number: 20170084327Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Applicant: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20170076760Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.Type: ApplicationFiled: July 15, 2016Publication date: March 16, 2017Inventor: Makoto YABUUCHI
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Publication number: 20170076783Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.Type: ApplicationFiled: July 15, 2016Publication date: March 16, 2017Inventors: Makoto YABUUCHI, Shinji TANAKA
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Publication number: 20170047129Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Applicant: Renesas Electronics CorporationInventor: Makoto YABUUCHI
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Patent number: 9548106Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.Type: GrantFiled: April 21, 2016Date of Patent: January 17, 2017Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
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Patent number: 9542999Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.Type: GrantFiled: December 28, 2015Date of Patent: January 10, 2017Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
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Publication number: 20160358645Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Applicant: Renesas Electronics CorporationInventors: Makoto YABUUCHI, Hidehiro FUJIWARA
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Publication number: 20160358667Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.Type: ApplicationFiled: August 18, 2016Publication date: December 8, 2016Inventors: Hidehiro FUJIWARA, Makoto YABUUCHI, Koji NII, Yoshikazu SAITO
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Patent number: 9508419Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.Type: GrantFiled: August 7, 2014Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventor: Makoto Yabuuchi
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Publication number: 20160329093Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.Type: ApplicationFiled: July 19, 2016Publication date: November 10, 2016Inventor: Makoto Yabuuchi
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Patent number: 9455022Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.Type: GrantFiled: July 18, 2014Date of Patent: September 27, 2016Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Hidehiro Fujiwara
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Patent number: 9449715Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.Type: GrantFiled: September 10, 2013Date of Patent: September 20, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii, Yoshikazu Saito
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Patent number: 9443575Abstract: The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell. Timing to negate at least two word lines (AWL, BWL), respectively coupled to two write ports, among the word lines is synchronized. Because synchronicity of writing different values to the memory cell is assured, by using a large number of such memory cells, it is possible to stably generate a PUF-ID without power on/off control.Type: GrantFiled: September 30, 2014Date of Patent: September 13, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Yabuuchi
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Patent number: 9424910Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.Type: GrantFiled: November 18, 2014Date of Patent: August 23, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Yabuuchi