Patents by Inventor Makoto Yasuda

Makoto Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100061697
    Abstract: A motion picture decoding device for decoding encoded motion pictures on a plurality of channels and synthesizing and reproducing the resultant images on the same screen, includes a decoder (511a, 511b) configured to decode an encoded motion picture on each channel, frame memories (520a, 520b) configured to store decoded frame image data, and a controller (151) configured to control these components. The controller (151), when a predetermined special playback mode is designated, performs a process, excluding, from display targets, frames having an evaluation index larger than or equal to a predetermined threshold, based on structure information, the evaluation index being based on a difference in a required-for-decoding number of frames between each channel.
    Type: Application
    Filed: April 7, 2008
    Publication date: March 11, 2010
    Inventor: Makoto Yasuda
  • Publication number: 20100021142
    Abstract: A moving picture decoding device according to the present invention includes: a determination unit configured to determine the header information and the compressed image data in the stream; a header information storage unit configured to temporarily store the header information determined by the determination unit; a header address storage unit configured to store a header end address indicating an end of header information in a picture, the header end address being an address of the header information storage unit; a compressed image storage unit configured to temporarily store the compressed image data determined by the determination unit; an image address storage unit configured to store an image end address indicating an end of compressed image data in the picture, the image end address being an address of the compressed image storage unit; a header analysis unit configured to analyze the header information for each picture, based on the header end address; and a decoding unit configured to decode the co
    Type: Application
    Filed: November 21, 2007
    Publication date: January 28, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masaki Minami, Shigeki Fujii, Kozo Kimura, Kosuke Yoshioka, Makoto Yasuda
  • Patent number: 7619364
    Abstract: To increase radiation intensity of deuterium lamp with continuous spectrum in UV region including vacuum UV in order to enable the lamp to illuminate wide area in high intensity. A pair of electrodes 7 and 8 is covered with dielectrics, placed outside of a UV transparent tubular discharge vessel 1 and plunged into the discharge vessel 1. There is a shield box 2 with a separator 3 between the electrodes 7 and 8 in the discharge vessel 1. Deuterium gas, hydrogen gas, mixture gas with deuterium, or mixture gas with hydrogen is enclosed in the discharge vessel 1 as discharge gas. A slit 4 is formed on the separator 3 along the axis of the discharge vessel 1 in order to squeeze the discharge path arising between the electrodes 7 and 8. The slit 4 makes radiant points continuous and then the lamp length would not be limited. When sine wave in high voltage is applied between the electrodes 7 and 8, dielectric-barrier discharge is caused.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: November 17, 2009
    Assignee: ORC Manufacturing Co., Ltd.
    Inventor: Makoto Yasuda
  • Publication number: 20090220181
    Abstract: A resin snap cage 4 comprises a resin-made circular main part 10, a plurality of pockets 11 provided in one axial end face of the circular main part 10, and a circular reinforcing member 12 installed concentrically at the other end face in an axial direction of the circular main part 10. While this reinforcing member 12 is circular along the circular main part 10, a sectional shape in a plane parallel to an axial direction is a rectangle. The reinforcing member 12 is embedded in a recessed portion formed at the other end face in an axial direction of the circular main part 10 to be integrated, an outside diameter surface 12a, an inside diameter surface 12b, and a pocket-side surface 12c of the reinforcing member 12 are covered with the circular main part 10, and a surface 12d thereof opposite to the pocket side is exposed.
    Type: Application
    Filed: November 20, 2006
    Publication date: September 3, 2009
    Applicant: NSK LTD.
    Inventors: Takiyoshi Yamada, Takahiko Uchiyama, Kenichi Iso, Junji Ono, Masahiro Harunaga, Kinji Yukawa, Makoto Yasuda, Jianjun Zhan, Nariaki Aihara
  • Patent number: 7577377
    Abstract: In a developing device of the present invention, the ratio of the volume of a two-ingredient type developer to the capacity of a space storing the developer is selected to range from 40% to 75%. A carrier, forming part of the developer, is made up of a core and a resinous coating layer formed on the core. The resinous coating layer contains conductive particles each having a tin dioxide layer formed on a core and an indium oxide layer formed on the tin dioxide layer and containing tin dioxide. The conductive particles are provided with an oil absorbing amount ranging from 10 ml/100 g to 300 ml/100 g.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: August 18, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Satoru Miyamoto, Makoto Yasuda
  • Publication number: 20090148186
    Abstract: A corona charger including a corona discharge electrode and a control electrode is provided. A layer including a zeolite, a conductive agent, and a binder resin is formed on a surface of the control electrode.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 11, 2009
    Applicant: RICOH COMPANY, LTD
    Inventors: Makoto Yasuda, Naohiro Toda, Yoshiki Yanagawa, Takeshi Orito, Shinji Nohsho
  • Publication number: 20080292981
    Abstract: This invention relates to image bearing member and an image forming apparatus that employs the image bearing member. The image bearing member contains an electroconductive substrate; a charge generation layer; a charge transport layer; a cross-linking surface protective layer, and a monomer having one radical polymerizable functional group with a charge transport structure. The cross-linking surface protective layer is formed by curing a monomer having at least three radical polymerizable functional groups without a charge transport structure. For the image bearing member, the ratio of the layer thickness of the cross linking surface protective layer to the layer thickness of the charge transport layer is from 0.7 to 1.3.
    Type: Application
    Filed: February 14, 2008
    Publication date: November 27, 2008
    Inventors: Naohiro Toda, Yoshiki Yanagawa, Takaaki Ikegami, Makoto Yasuda, Takeshi Orito
  • Publication number: 20080203493
    Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 28, 2008
    Applicant: Fujitsu Limited
    Inventor: Makoto Yasuda
  • Publication number: 20080160686
    Abstract: A semiconductor device includes a semiconductor substrate, a field effect transistor (FET), contact plugs, a resistive element (specific member) and interconnects. Contact plugs are connected to the FET. A resistive element is provided in the layer (lowermost layer of interconnect layer) that also includes the contact plug. The contact plug and the resistive element are formed of the same material. Portions of the upper surface of the resistive element are connected to the interconnects.
    Type: Application
    Filed: October 16, 2007
    Publication date: July 3, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Ikuo NAKAMATSU, Makoto YASUDA, Toshiyuki TAKEWAKI, Yasutaka NAKASHIBA, Shinichi UCHIDA
  • Patent number: 7340202
    Abstract: An image forming apparatus and process cartridge that achieves extended operating life of a two-component developer without generating such problems as toner scattering, etc. either in the initial period or over time. The gap between the image support member and the developer support member is set to 0.3±0.1 mm. A substance having a resin cover layer on the surface of a core material is used as the carrier. The resin cover layer provides a conductive covering layer having a tin dioxide layer on the surface of base particles and an indium oxide layer, and contains conductive particles formed such that the oil adsorption is 10 to 300 mL/100 g. A substance that provides a bonding resin including a hybrid resin having vinyl polymers and polyester polymers is used as the toner. The amount of hybrid resin contained in relation to the amount of releasing agent is set to the range of 0.5 to 3.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: March 4, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Satoru Miyamoto, Makoto Yasuda
  • Publication number: 20070285015
    Abstract: To increase radiation intensity of deuterium lamp with continuous spectrum in UV region including vacuum UV in order to enable the lamp to illuminate wide area in high intensity. A pair of electrodes 7 and 8 is covered with dielectrics, placed outside of a UV transparent tubular discharge vessel 1 and plunged into the discharge vessel 1. There is a shield box 2 with a separator 3 between the electrodes 7 and 8 in the discharge vessel 1. Deuterium gas, hydrogen gas, mixture gas with deuterium, or mixture gas with hydrogen is enclosed in the discharge vessel 1 as discharge gas. A slit 4 is formed on the separator 3 along the axis of the discharge vessel 1 in order to squeeze the discharge path arising between the electrodes 7 and 8. The slit 4 makes radiant points continuous and then the lamp length would not be limited. When sine wave in high voltage is applied between the electrodes 7 and 8, dielectric-barrier discharge is caused.
    Type: Application
    Filed: May 16, 2007
    Publication date: December 13, 2007
    Applicant: ORC MANUFACTURING CO., LTD.
    Inventor: Makoto YASUDA
  • Publication number: 20070140749
    Abstract: An improved developing device for developing latent images to toner images is provided for stabilizing the amount of the developer on the developing bearing member, in which the amount of toner particles consumed in one second for the development process “a” (mg/sec) and circumferential velocity of the surface of the developer bearing member “b” (m/sec) are arranged to satisfy the following relationships (1) and (2) at the condition in which the amount of the developer after 20 hours of rotation of the developer bearing member exceeds the amount of the developer before rotation: 45 mg/m<a/b??(1) a/b<110 mg/m??(2).
    Type: Application
    Filed: December 8, 2006
    Publication date: June 21, 2007
    Inventors: Satoru Miyamoto, Makoto Yasuda, Tomio Kondou, Shinichiro Yagi, Kousuke Suzuki, Hitoshi Iwatsuki
  • Patent number: 7071116
    Abstract: The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3M? cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: July 4, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Makoto Yasuda
  • Publication number: 20060120767
    Abstract: An image forming apparatus and process cartridge that achieves extended operating life of a two-component developer without generating such problems as toner scattering, etc. either in the initial period or over time. The gap between the image support member and the developer support member is set to 0.3±0.1 mm. A substance having a resin cover layer on the surface of a core material is used as the carrier. The resin cover layer provides a conductive covering layer comprising a tin dioxide layer on the surface of base particles and an indium oxide layer, and comprises conductive particles formed such that the oil adsorption is 10 to 300 mL/100 g. A substance that provides a bonding resin comprising a hybrid resin having vinyl polymers and polyester polymers is used as the toner. The amount of hybrid resin contained in relation to the amount of releasing agent is set to the range of 0.5 to 3.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 8, 2006
    Inventors: Satoru Miyamoto, Makoto Yasuda
  • Publication number: 20060099009
    Abstract: In a developing device of the present invention, the ratio of the volume of a two-ingredient type developer to the capacity of a space storing the developer is selected to range from 40% to 75%. A carrier, forming part of the developer, is made up of a core and a resinous coating layer formed on the core. The resinous coating layer contains conductive particles each having a tin dioxide layer formed on a core and an indium oxide layer formed on the tin dioxide layer and containing tin dioxide. The conductive particles are provided with an oil absorbing amount ranging from 10 ml/100 g to 300 ml/100 g.
    Type: Application
    Filed: October 25, 2005
    Publication date: May 11, 2006
    Inventors: Satoru Miyamoto, Makoto Yasuda
  • Patent number: 7002201
    Abstract: The present invention includes one wiring or a plurality of wirings and an MIM capacitor formed by capacity coupling of a lower electrode which is connected to an upper surface of the wiring(s) and an upper electrode. The lower electrode is comprised of a material preventive of diffusion of a material of the wiring(s), and it embraces the wiring(s).
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: February 21, 2006
    Assignee: Fujitsu Limited
    Inventor: Makoto Yasuda
  • Publication number: 20050199933
    Abstract: The semiconductor device comprises a device isolation region 14 formed in a semiconductor substrate 10, a lower electrode 16 formed in a device region 12 defined by the device isolation region and formed of an impurity diffused layer, a dielectric film 18 of a thermal oxide film formed on the lower electrode, an upper electrode 20 formed on the dielectric film, an insulation layer 26 formed on the semiconductor substrate, covering he upper electrode, a first conductor plug 30a buried in a first contact hole 28a formed down to the lower electrode, and a second conductor plug 30b buried in a second contact hole 28b formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode 20 is not formed in the device isolation region 14, whereby the short-circuit between the upper electrode 20 and the lower electrode 16 in the cavity can be prevented. Thus, a capacitor of high reliability can be provided.
    Type: Application
    Filed: August 25, 2004
    Publication date: September 15, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Makoto Yasuda, Akiyoshi Watanabe, Yoshihiro Matsuoka
  • Publication number: 20040259374
    Abstract: The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3M&OHgr; cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).
    Type: Application
    Filed: June 16, 2004
    Publication date: December 23, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Makoto Yasuda
  • Patent number: 6780705
    Abstract: A semiconductor device having: a semiconductor substrate having first and second regions defined in a principal surface of the semiconductor substrate; a first underlying film formed in the second region; a first lamination structure formed in a partial area of the first region, the first lamination structure having a conductive film and an insulating film stacked in this order from the substrate side; and a second lamination structure formed on the first underlying film and having a conductive film and an insulating film stacked in this order from the substrate side, wherein the insulating films of the first and second lamination structures are made of the same material and the height of the upper surface of the second lamination structure as measured from the principal surface of the semiconductor substrate is equal to or lower than the height of the upper surface of the first lamination structure as measured from the principal surface of the semiconductor substrate.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventor: Makoto Yasuda
  • Patent number: 6754275
    Abstract: A smooth reproduced picture is produced at inverse playback, without losing of naturality of display. Picture output candidate frames are decided such that intervals between frame are uniform on a time axis at a normal playback. When the candidate frame exists in a group of pictures (GOP) preceding a GOP which is presently displayed and a number of frames in the GOP is unknown, a frame among one of a last or a second to last I or P coded frame in the GOP, which is nearer to a true picture output frame is decided as a picture output candidate frame.
    Type: Grant
    Filed: November 26, 1999
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Yasuda, Tadashi Shibata