Abstract: A resin pipe joint (1, 11) includes a tubular joint body portion (2, 12) defining an internal flow path (P) the internal flow path being configured to allow a fluid to flow therein; and two or more welding end portions (3-3c, 13a, 13b) respectively provided at two or more opening portions (A1-A3) of the internal flow path (P), each of the welding end portions being configured to be welded to an abutting welding end portion of other resin piping member, wherein the internal flow path (P) comprises: one of a branched point (Bp) that branches the internal flow path (P) into two or more portions; a curved point (Cp) that bends the internal flow path (P); and an internal diameter transition point (Tp) that changes an internal diameter of the internal flow path, in mid-way of the internal flow path, and wherein a length (Lh) from the branched point (Bp), the curved point (Cp) or the inner diameter transition point (Tp) to an end face of the welding end portion (3-3c, 13a, 13b) is shorter than half of a straight dis

Abstract: This invention relates to a resin pipe joint (1, 11, 21), which includes: a tubular joint body portion (2, 12, 22) having an internal flow path (P) for allowing a fluid to flow therein; and two or more welding end portions (3a-3c, 13a, 13b, 23a, 23b) which are respectively provided at two or more opening portions of the internal flow path (P) and which are welded while being butted against end portions of other resin tube members or end portions of other resin pipe joints, wherein the flow path cross-sectional area of the internal flow path (P) in the joint body portion (2, 12, 22) is constant at least in portions which are adjacent to the welding end portions (3a-3c, 13a, 13b, 23a, 23b) and whose outer diameters are straight.

Abstract: Provided are: a cleaning agent for a denitration catalyst; and a denitration catalyst regeneration method and a denitration catalyst regeneration system which make it possible to efficiently remove matter adhering to a surface of a catalyst and to greatly restore catalytic performance. The regeneration method includes: a prewashing step (S12) of washing a denitration catalyst with water; a liquid agent cleaning step (S14) of immersing the denitration catalyst washed with water in a liquid agent containing an inorganic acid and a fluorine compound; a step of recovering the denitration catalyst from the liquid agent; and a finish washing step (S16) of washing the denitration catalyst recovered from the liquid agent with a finish cleaning liquid which is water or sulfamic acid-containing water.

Abstract: The plurality of protective grooves 225 has openings 2231 wider than thicknesses of the edge portions of the substrates W to allow the edge portions of the substrates W to be inserted. The edge portions of the substrates W are inserted into the protective grooves 225 in a non-contact state in which a space is formed between the edge portions of the substrates W and a groove forming surface 2221 of the substrate edge portion protective portion 222 on which the protective grooves 225 are formed when the container main body opening portion is closed by the lid body and the edge portions of the substrates W are not in contact with the groove forming surface 2221.

Abstract: In a liquid crystal display device, it is determined whether or not image data inputted from the outside has changed from image data of the previous frame by comparing those image data with respect to each line. As a result, when it is determined that the image data has changed, an entire screen is not rewritten, but image data from a top of a screen as a fixed position to a last line with the image data having changed are read from a frame memory and written into a pixel formation portion. Accordingly, of the screen for one frame, a screen from a top thereof to the last line where the image change has been detected is updated, and on subsequent lines, an image of the previous frame is continuously displayed.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

Abstract: In a liquid crystal display device, it is determined whether or not image data inputted from the outside has changed from image data of the previous frame by comparing those image data with respect to each line. As a result, when it is determined that the image data has changed, an entire screen is not rewritten, but image data from a top of a screen as a fixed position to a last line with the image data having changed are read from a frame memory and written into a pixel formation portion. Accordingly, of the screen for one frame, a screen from a top thereof to the last line where the image change has been detected is updated, and on subsequent lines, an image of the previous frame is continuously displayed.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

Abstract: The end portion is melted by a heater and is welded to an end portion of another weld fitting. Positioning scales exist at equal intervals in a peripheral direction of an outer periphery of the fitting main body portion, in an outer peripheral portion of the fitting main body portion, the outer peripheral portion being not clamped by a clamp portion, and in a portion at an opposite side to the end portion with respect to an outer peripheral portion of the fitting main body portion, the outer peripheral portion being clamped by the clamp portion. The weld fitting is welded to the other weld fitting so that the positioning scale is matched with a reference mark provided on the clamp portion.

Abstract: A shift register is disclosed which includes, at respective stages, unit circuits (11) each including (i) a flip-flop (11a) including first and second CMOS circuits and (ii) a signal generation circuit (11b) for generating an output signal (SROUTk) for the current stage with use of an output (Q, QB) of the flip-flop (11a), the shift register including a floating control circuit (11c) between a gate terminal of an output transistor (Tr7) of the signal generation circuit (11b) and a Q terminal. This makes it possible to reduce a circuit scale of a display driving circuit without causing a shift register to malfunction.

Abstract: A retention circuit (22) corresponding to each stage of a shift register is configured such that, when SROUT(k?1) is active, an input terminal of an inverter (INV1) and an output terminal of an inverter (INV2) are electrically connected to each other and an output terminal of the inverter (INV1) and an input terminal of the inverter (INV2) are connected to each other. This makes it possible to reduce a circuit scale of a display driving circuit without causing any malfunction of the display driving circuit.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.

Abstract: In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

Abstract: This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.

Abstract: A flip-flop circuit (11a) includes: an input transistor (Tr19) having a gate terminal thereof connected to an SB terminal, a source terminal thereof connected to an RB terminal, and a drain terminal thereof connected to a first CMOS circuit and a second CMOS circuit; a power supply (VSS) which is connected to the first CMOS circuit or the second CMOS circuit and, when an SB signal is turned to be active, is connected to the RB terminal; and a regulator circuit (RC). With the arrangement, a compact flip-flop and a compact shift register employing the flip-flop are provided, without causing malfunction of the flip-flop and the shift register.

Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.

Abstract: Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.

Abstract: Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.

Abstract: A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.