Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL signal and a first mixer coupled to receive a first signal from the VCO and a signal from one of the antennas, and a second receive path integrated separately from the first receive path including a second mixer coupled to receive a second signal from the VCO and a signal from the other antenna. By utilizing the output of the VCO to tune the first and second mixers in the first and second receive paths to the same phase and frequency, control of the multiple antenna receive paths may be optimized.

Abstract: A dual receive path for a wireless communication device having one synthesizer that drives one or two receive VCOs.

Abstract: A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.

Abstract: An amplifier includes a Darlington transistor pair and a biasing network to increase bias currents in an input transistor.

Abstract: A loop filter for a frequency synthesizer provides a lower frequency pole with a smaller capacitor than conventional filters. The loop-filter comprises a resistor and a smaller capacitor in a series-feedback path, and a transconductor to sense a voltage across the resistor to either source or sink additional current proportional to the sensed voltage. The transconductor and the smaller capacitor may provide a larger capacitance. The loop filter also may comprise an operational amplifier having the smaller capacitor and the resistor in the series-feedback path to receive pulses from a charge pump. The filter may integrate the pulses and may generate a control voltage related to a width of the pulses.

Abstract: An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Abstract: A system for two processors communicating though unidirectional links by embedding a strobe signal into the data by providing differential signals with different common mode signal levels.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide interference detection and cancellation is provided. The apparatus may include a first antenna coupled to a first receiver, and a second antenna coupled to a second receiver, wherein the second antenna has a radiation pattern different than a radiation pattern of the first antenna.

Abstract: A dual receive path for a wireless communication device having one synthesizer that drives one or two receive VCOs.

Abstract: A system for two processors communicating though unidirectional links by embedding a strobe signal into the data by providing differential signals with different common mode signal levels.

Abstract: The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.

Abstract: An electrical circuit which includes a filter bypass mode. The circuit includes an amplifier including an inverting terminal, a noninverting terminal and an output terminal, at least one first capacitor coupled to the inverting terminal of the amplifier through at least one first switch, and, at least one second capacitor coupled to the noninverting terminal of the amplifier through at least one second switch. The electrical circuit provides filtering when the first and second switches are in a first state, and when the first and second switches are in a second state, the electrical circuit provides substantially no filtering.

Abstract: A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams.

Abstract: The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.

Abstract: The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.

Abstract: The present invention is directed to an integrated circuit having a current supply circuit for supplying a reference current and a signal current; at least one current copier circuit for creating a copy of the reference current and a copy of the signal current; an amplifying circuit connected to the reference supply circuit, the signal supply circuit, and the current copier circuit. The amplifying circuit is configured with the current copier circuit to compare the copy of the reference current to the signal current and to compare the copy of the signal current to the reference current and to generate a comparison signal based upon the comparisons. The present invention may also include an output circuit connected to the amplifying circuit for receiving the comparison signal and generating an output signal and a current mode circuit for receiving the output signal.

Abstract: A start-up circuit for supplying current to an analog circuit. The start-up circuit comprises a capacitor connected to a current mirror. A power-up signal input to the start-up circuit causes the capacitor to discharge to the current mirror thereby causing the current mirror to provide a current to the analog circuit.