Abstract: A start-up circuit for providing current to an analog circuit wherein the analog circuit contains an operational amplifier. The start-up circuit makes use of normal operation of the analog circuit to perform a power-up function. A node being powered up is at substantially all times controlled by the operational amplifier, minimizing performance variation resulting from process and temperature variations.

Abstract: A method and apparatus are disclosed for improving the operation of an analog-to-digital converter (“ADC”). A separate “clean” oscillator clock is to be used in combination with a “noisy” ADC clock being regulated by a phase-locked-loop (PLL) circuit. The “noisy” ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., “clean”) frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.

Abstract: The voltage-controlled current source receives a control voltage from an operational amplifier which itself receives a reference voltage at one input from a bias circuit. The voltage-controlled current source applies current to the base of the amplifier's main transistor. The base of the transistor is also coupled to the input node of the amplifier through a DC-blocking capacitor and through a feedback loop to the other input of the operational amplifier. The voltage-controlled current source operates to maintain the voltage at the base of the transistor relatively constant for a wide range of input signal levels. As a result, the amplifier is able to operate at relatively low power supply voltages (e.g., as low as 2V) without suffering from premature gain compression at relatively high input signal levels (e.g., as high as 0.4V).

Abstract: A method and apparatus for tuning an analog filter that is embodied in a larger circuit in which the analog input signal to the filter is, at some point prior to the filter, in digital form. The digital version of the input signal to the filter is stored in memory. The output signal from the filter corresponding to the stored input signal is digitized and compared to the stored digital input signal to the filter. Based on the known input signal and the known desired frequency characteristics of the filter, the desired output signal is a known quantity. If the actual output signal differs from the expected output signal, the filter is tuned accordingly. The process may be performed continually on all input data or on discrete sections of the input data.

Abstract: The present invention is embodied in a method and apparatus for sensing the logic state of a flash memory cell utilizing a current mode sense amplifier circuit that is less susceptible to noise. The sense amplifier consists of a controlled current source with mirroring, an integrator and a comparator. In the sensing phase, a cell with a stored low logic level will cause a first current to flow. The first current will be mirrored by a second current. The second current is integrated and compared against a reference voltage to determine the logic state of the cell. By integrating and comparing the mirrored current, the sense amplifier circuit is less susceptible to spurious signals caused by noise.