Abstract: A method for managing a processor, the processor comprising a common supply rail and processor cores being connected to the common supply rail, wherein each processor core comprises a core unit, wherein the method comprises detecting idle state exits indicated by the core units; and delaying a command execution of at least one of the core units indicating an idle state exit when the number of idle state exits exceeds a predetermined threshold idle state exit number may reduce voltage droops due to several processor cores leaving the idle state at the same time.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.

Abstract: A zone power cap for a power management zone that defines a limit of power consumption for the power management zone is determined. The power management zone comprises a plurality of components, wherein the power management zone is associated with a controller. A set of one or more characteristics of a workload associated with the power management zone is determined. A component power cap for one or more of the plurality of components is set based, at least in part, on the set of one or more characteristics of the workload and the zone power cap.

Abstract: A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory. The memory stores program code, which, when executed on the processor, performs an operation for adjusting a frequency of a processor. The operation includes inhibiting one or more processor cores from exiting an idle state. The operation further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The operation also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The operation includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.

Abstract: A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.