Patents by Inventor Mami Toda

Mami Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD)
    Publication number: 20140327064
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
    Patent number: 8815678
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 26, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • SEMICONDUCTOR DEVICE HAVING A THIN FILM CAPACITOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20120261735
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1?x)O.sub.2 (0<x<1), (Zr.sub.y, Ti.sub.1?y)O.sub.2 (0<y<1), (Hf.sub.z, Ti.sub.1?z)O.sub.2 (0<z<1), (Zr.sub.k, Ti.sub.l, Hf.sub.m)O.sub.2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure
    Patent number: 8212299
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1?x)O2(0<x<1), (Zry, Ti1?y)O2(0<y<1), (Hfz, Ti1?z)O2(0<z<1), (Zrk,Til, Hfm)O2(0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0
    Patent number: 8169013
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Semiconductor device and method for manufacturing same
    Patent number: 7829925
    Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: November 9, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Sakoh, Mami Toda
  • Semiconductor memory device
    Patent number: 7737481
    Abstract: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 15, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Sakoh, Mami Toda
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20080197392
    Abstract: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 21, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takashi SAKOH, Mami TODA
  • METHOD FOR FABRICATING A METAL-INSULATOR-METAL (MIM) CAPACITOR HAVING CAPACITOR DIELECTRIC LAYER FORMED BY ATOMIC LAYER DEPOSITION (ALD)
    Publication number: 20080064147
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 13, 2008
    Applicant: NEC CORPORATION
    Inventors: Toshihiro IIZUKA, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20080048228
    Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 28, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takashi SAKOH, Mami TODA
  • Method for fabricating a metal insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
    Publication number: 20070152256
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Application
    Filed: December 12, 2006
    Publication date: July 5, 2007
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Semiconductor device having a thin film capacitor and method for fabricating the same
    Publication number: 20050051824
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (O<z<l), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: October 18, 2004
    Publication date: March 10, 2005
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Semiconductor device and method of manufacturing the same
    Publication number: 20040232558
    Abstract: A semiconductor device has an insulating film. An interconnect groove or a via hole is formed in the insulating film. An interconnect pattern or a via hole is buried in the interconnect groove or the via hole. A substantially flat hard mask is formed on the interconnect pattern. The hard mask is provided with an opening portion having a width narrower than a space between adjacent interconnect patterns and is made of a material that is etched selectively with the insulating film.
    Type: Application
    Filed: January 20, 2004
    Publication date: November 25, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Mami Toda
  • Semiconductor device having a thin film capacitor and method for fabricating the same
    Publication number: 20020190294
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1−x)O2 (0<x<1), (Zry, Ti1−y)O2 (0<y<1), (Hfz, Ti1−z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 19, 2002
    Inventors: Toshihiro Iizuka, Tomeo Yamamoto, Mami Toda, Shintaro Yamamichi