Semiconductor device having a thin film capacitor and method for fabricating the same
In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (O<z<l), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
The present invention relates to a semiconductor device having a thin film capacitor and a method for fabricating the same.
Heretofore, in a general purpose DRAM, Ta2O5 having a high dielectric constant has been considered as a capacitor dielectric film in a memory cell. In this case, it is an ordinary practice that a lower electrode of a capacitor is formed of a polysilicon layer which can be formed to have a concavo-convex surface (for example, so called HSG (hemi-spherical grain) structure) in order to increase a capacitance per a unitary area. In order to form this polysilicon layer, a high temperature process on the order of 700 to 900 degrees Celsius is required.
On the other hand, in a logic mixed DRAM in which a logic section and a memory section are formed on the same chip, gate electrodes and source/drain diffused regions in the logic section are required to be provided with a cobalt (Co) silicide for a speedup of transistors.
The cobalt silicide layer can realize a low resistance, however, if the temperature is elevated, aggregation occurs in the cobalt silicide layer so that the resistance value of the gate electrodes and the diffused layers increases. Therefore, in a process after formation of the cobalt silicide layer, the process temperature cannot be elevated. For example, in the generation of the gate length of 0.15 micron, about 600 degrees Celsius is an upper limit.
Accordingly, if Ta2O5 is used to form a capacitor dielectric film in the memory section of the logic mixed DRAM and if a polysilicon layer is used to form a lower capacitor electrode, a high temperature process is required to form the polysilicon layer, with the result that the transistors in the logic section become deteriorated through the high temperature process. Therefore, in the generation of the gate length of 0.15 micron and in succeeding generations, it is not possible to use the polysilicon for the lower capacitor electrode. Under this situation, there is a demand for constitute the electrode of the capacitor with a metal or a metal nitride, for example, TiN (titanium nitride), W (tungsten) or Ru (ruthenium), which can be formed at a low temperature of not greater than 500 degrees Celsius where no aggregation occurs in the cobalt silicide.
Now, explanation will be made on a conventional method for forming a thin film capacitor, using a metal or a metal nitride for the lower capacitor electrode and also using Ta2O5 for the capacitor dielectric film.
A lower electrode of TiN, W or Ru is formed by a CVD (chemical vapor deposition) or a PVD (physical vapor deposition), and then, a Ta2O5 capacitor dielectric film is formed by a thermal CVD process. Thereafter, in order to reduce a leakage current in the Ta2O5 capacitor, a post anneal is carried out with a RTO (rapid thermal oxidation) or a UV-O3 oxidation at a temperature of not less than 500 degrees Celsius. Furthermore, an upper electrode of TiN or another is formed by the CVD process or the PVD process, and then, a patterning is carried out to have a desired shape. Thus, the thin film capacitor of a MIM structure having the capacitor dielectric film formed of Ta2O5 is obtained.
Furthermore, in a LSI chip, it is considered to form a high dielectric constant thin film capacitor above interconnections in the LSI, so as to use it as a decoupling capacitor. The decoupling capacitor is provided to compensate for a voltage drop which is caused for a parasite inductance existing between a power supply and interconnections of the LSI.
Referring to
As shown in
In the case of forming a high dielectric constant thin film capacitor over the uppermost interconnection layer in the semiconductor device to use it as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor,
As mentioned above, in the conventional thin film capacitor having the lower electrode formed of TiN, W or Ru and the capacitor dielectric film of Ta2O5, it is necessary to carry out the post-anneal in an oxidizing atmosphere since the leakage current is large in a condition just after the formation of Ta2O5. However, because of this post anneal, the lower electrode layer is oxidized so that a low dielectric constant film is formed. As a result, even if the thickness of the Ta2O5 film is reduced, a large capacitance cannot be obtained.
In addition, because of the oxidation occurring in the post anneal, a concavo-convex or a peeling occurs in the lower electrode layer, with the result that the yield of production lowers.
Furthermore, as shown in
On the other hand, in the case that a high dielectric constant thin film capacitor is formed over the uppermost interconnection layer in the semiconductor device and is used as the decoupling capacitor, the demand of a low inductance and a large capacitance is satisfied with a one-chip feature and use of a high dielectric constant capacitor, but the present method for forming the thin film capacitor has a problem.
It has been proposed to use Ta2O5, SrTiO3 and (Ba, Sr)TiO3 formed by the PVD process or the CVD process, for the capacitor dielectric film of the above mentioned thin film capacitor. However, in order to obtain a capacitor dielectric film of an excellent quality having a large capacitance in the conventional method utilizing the PVD or CVD process, a high temperature of not less than 400 degrees Celsius is required. In addition, in order to reduce the leakage current, it is also necessary to carry out the post anneal in the oxidizing atmosphere at the temperature of not less than 450 degrees Celsius.
Furthermore, recently, a copper wiring conductor is used for interconnection. Therefore, in the case that a capacitor is formed over the uppermost interconnection layer, if the temperature is elevated to not less than 450 degrees Celsius, the interconnection layer is oxidized, with the result that the characteristics is deteriorated and the yield of production lowers.
In other word, the conventional method for forming the thin film capacitor can realize a large-capacitance, low-inductance, one-chip decoupling capacitor which meet with the speedup of the LSI.
BRIEF SUMMARY OF THE INVENTIONAccordingly, it is an object of the present invention to provide a thin film capacitor and a method for forming the same, which have overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a capacitor which can realize a large capacitance and a small leakage current as a capacitor for a DRAM cell in a memory section of a semiconductor device having the memory section and a logic section formed on the same chip, without deterioration of a transistor characteristics attributable to deterioration in a silicide layer formed in gate electrodes and on source/drain diffused layer regions in the semiconductor device.
Still another object of the present invention is to provide a semiconductor device having the above mentioned capacitor formed after an interconnection layer is formed (namely, above the interconnection layer) and a method for fabricating the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1).
According to another aspect of the present invention, there is provided a semiconductor device including a transistor having a gate electrode and source/drain diffused layers having a refractory metal silicide, wherein a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film, which is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and which is provided on an insulator film formed on the source/drain diffused layer.
According to still another aspect of the present invention, there is provided a semiconductor device wherein a capacitor of a MIM (metal-insulator-metal) structure having a capacitor dielectric film, which is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and which is provided on an insulator film formed on an interconnection.
According to a further aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, after formation of the capacitor dielectric film, carrying out a heat treatment at a temperature not lower than a film deposition temperature in the atomic layer deposition.
According to a still further aspect of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, M<1, k+l+m=1), and, after formation of the capacitor dielectric film, carrying out a heat treatment at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of a refractory metal silicide occurs in a gate electrode and source/drain diffused layer regions in the case that the refractory metal silicide is provided in the gate electrode and the source/drain diffused layer regions.
According to a further aspect of the present invention, there is provided a method for fabricating a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure formed on an insulator film formed on an interconnection, comprising the steps of forming a lower electrode of the capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1), and then, forming an upper electrode on the capacitor dielectric film.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Now, embodiments of the present invention will be described with reference to the drawings.
Referring to
The first embodiment is a thin film capacitor of a MIM (metal-insulator-metal) structure, provided in a semiconductor device. This thin film capacitor includes a lower electrode 1, a capacitor dielectric film 2 and an upper electrode 3 stacked in the named order. Each of the upper electrode 3 and the lower electrode 1 is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. The capacitor dielectric film 2 is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, 1, m<1, k+l+m=1), and formed by means of an atomic layer deposition (abbreviated to “ALD”).
Here, (Zrx, Hf1-x)O2 (0<x<1) is an oxide of a solid solution of Zr and Hf. (Zry, Ti1-y)O2 (0<y<1) is an oxide of a solid solution of Zr and Ti. (Hfz, Ti1-z)O2 (0<z<1) is an oxide of a solid solution of Hf and Ti. (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1) is an oxide of a solid solution of Zr, Ti and Hf.
Here, a method for forming the thin film capacitor in the case that the capacitor dielectric film is formed of ZrO2, will be described. First, a lower electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that a lower electrode 1 is formed.
Then, a capacitor dielectric film is formed of ZrO2 by means of the ALD process.
The ZrO2 thin film is deposited by using ZrCl4 as a starting material for Zr and H2O as an oxygen material, under a deposition temperature of 200 to 400 degrees Celsius.
First, ZrCl4 is supplied as a starting material into a chamber of the ALD apparatus, so that only a one-atom layer is deposited on a surface of the lower electrode thin film by causing a reaction. Next, the supply of ZrCl4 is stopped, and an inert gas represented by Ar or N2 is introduced into the chamber as a purge gas so that an excessive unreacted ZrCl4 is removed.
Thereafter, H2O is supplied to replace a Cl group which terminates Zr grown on the surface of the lower electrode thin film, with an OH group of H2O. In this process, HCl is produced as a reaction subproduct. Then, the supply of H2O is stopped, and the inert gas represented by Ar or N2 is introduced into the chamber as the purge gas so that an unreacted H2O and the reaction subproduct HCl are removed.
Then, ZrCl4 is supplied again so that only another one-atom layer is deposited. The supply of ZrCl4 is stopped, and the purge gas is produced so that an unreacted ZrCl4 and the reaction subproduct HCl are removed.
In this manner, a cycle of the ZrCl4 supply, the purge, the H2O supply and the purge sequentially carried in the named order, is repeated necessary times, until the capacitor dielectric film 2 of ZrO2 having the film thickness of 5 to 15 nm is obtained.
After the ZrO2 thin film is formed, an upper electrode thin film having a film thickness of 5 to 50 nm is formed of at least one material selected from the group consisting of TiN, Ti, W, WN, Pt, Ir, Ru, by means of a PVD process, a CVD process or a ALD process, and then, is patterned into a desired shape, so that an upper electrode 3 is formed. Thus, the thin film capacitor is obtained.
The thin film capacitor formed as mentioned above has a small leakage current and a large capacitance, because the capacitor dielectric film is formed of ZrO2 having a high electrical insulation property and a large dielectric constant, and because a leakage current increase is small even if the film thickness of ZrO2 is reduced.
In addition, if the ZrO2 thin film is formed by the ALD process, it is possible to carry out a film formation at a low temperature and to omit a post anneal which is carried out in an oxidizing atmosphere. Therefore, it is possible to avoid the drop of the capacitance, the increase of the leakage current and the drop in the yield of production, caused by oxidation of the lower electrode.
Referring to
In the above mentioned embodiment, the capacitor dielectric film is formed of ZrO2 deposited by the ALD process. However, a similar advantage can be obtained in the case that the capacitor dielectric film is formed of at least one material selected from the group consisting of HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1).
In the case that the capacitor dielectric film is formed of HfO2, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
In the case that the capacitor dielectric film is formed of (Zrx, Hf1-x)O2, ZrCl4 is used as a starting material for Zr, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
In the case that the capacitor dielectric film is formed of (Zry, Ti1−y)O2, ZrCl4 is used as a starting material for Zr, TiCl4 is used as a starting material for Ti, and H2O is used as an oxygen material.
In the case that the capacitor dielectric film is formed of (Hfz, Ti1-z)O2, HfCl4 is used as a starting material for Hf, TiCl4 is used as a starting material for Ti, and H2O is used as an oxygen material.
In the case that the capacitor dielectric film is formed of (Zrk, Til, Hfm)O2, ZrCl4 is used as a starting material for Zr, TiCl4 is used as a starting material for Ti, HfCl4 is used as a starting material for Hf, and H2O is used as an oxygen material.
Now, a second embodiment of the present invention will be described.
According to this second embodiment, in a thin film capacitor of a MIM structure having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), deposited by means of the ALD process, an anneal is carried out after formation of the capacitor dielectric film.
The thin film capacitor of the MIM structure in accordance with the first embodiment having the capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<Z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), has a small leakage current and a large capacitance, in comparison with the thin film capacitor having the capacitor dielectric film formed of Ta2O5, and therefore, can be satisfactorily used as a memory capacitor in a DRAM cell. However, when the film thickness of the capacitor dielectric film is decreased, the capacitance increase is small (namely, the decrease of teq is small), and on the other hand, the leakage current increases.
Referring to
The reason for this is considered as follows: Just after the deposition of the ZrO2 thin film, a ZrO2 boundary layer having poor crystallinity exists, which act as a low dielectric constant layer. Therefore, even if the film thickness is decreased, the low dielectric constant layer contribution is large, with the result that the capacitance of the capacitor as a whole cannot be correspondingly increased. On the other hand, the leakage current increases with the decrease of the film thickness.
In this second embodiment, on the other hand, in the thin film capacitor formed in accordance with the first embodiment, namely, in the thin film capacitor of the MIM structure having the capacitor dielectric film formed of the ZrO2 thin film formed by the ALD process, the anneal is carried out at a temperature of 300 to 700 degrees Celsius after the deposition of the ZrO2 thin film. As a result, a further large capacitance and a small leakage current are realized in the thin film capacitor.
As mentioned above, the thin film capacitor having the ZrO2 thin film deposited on a metal electrode by the ALD process can be used as a memory capacitor in the DRAM cell. However, in order to meet with the demand for a further microminiaturization and a further high integration, it is preferred to obtain a further large capacitance and a small leakage current.
The inventors of the present application uncovered that if an ZrO2 thin film is only deposited on a metal electrode by the ALD process, an amorphous ZrO2 layer region exists at a boundary between the lower electrode and the ZrO2 layer, and it is not possible to obtain a characteristics intrinsic to the MIM structure thin film capacitor having the capacitor dielectric film of ZrO2. Namely, since the amorphous layer functions as a low dielectric constant layer in the MIM structure thin film capacitor, the obtained capacitance drops.
Furthermore, the inventors of the present application uncovered and confirmed that the amorphous ZrO2 layer is crystallized by carrying out the anneal after the deposition of the ZrO2 layer. With this crystallization, the ZrO2 layer is homogenized, so that the above mentioned low dielectric constant boundary layer is removed. As a result, it was confirmed that a further large capacitance and a small leakage current are obtained in comparison with the case that no anneal was carried out.
For example, the ZrO2 capacitor dielectric film is deposited on the lower electrode of TiN by the ALD process at a temperature of 200 to 400 degrees Celsius, and thereafter, for example, the upper electrode of TiN is formed, and then, is patterned into a desired shape, so that the MIM thin film capacitor is obtained. Thereafter, the MIM thin film capacitor thus obtained is annealed at a temperature which is not lower than a ZrO2 layer deposition temperature and which is in a range of 300 to 700 degrees Celsius.
Incidentally, the above mentioned amorphous layer is formed when the capacitor dielectric film is deposited, and the anneal may be carried out at any time after the deposition of the capacitor dielectric film. For example, a similar advantage can be obtained even if the anneal is carried out immediately after the deposition of the capacitor dielectric film or even if the anneal is carried out after the formation of the upper electrode.
In addition, the atmosphere in which the anneal is carried out is not important, but it is preferable to use a non-oxidizing atmosphere which does not cause a characteristics deterioration attributable to oxidation of the low electrode material, namely, N2, Ar, He, or a forming gas (H2+N2).
Referring to
Referring to
As seen from the above, in the thin film capacitor of the second embodiment, the low dielectric constant layer (ZrO2 boundary layer having poor crystallinity) existing just after the deposition of the ZrO2 thin film, is improved in crystallinity by the anneal, so that it no longer functions as the low dielectric constant layer. As a result, the capacitance is increased (namely, teq is decreased). In addition, since crystallinity is improved in the whole of the ZrO2 thin film, the leakage current is decreased.
In the above mentioned second embodiment, the capacitor dielectric film is formed of ZrO2. However, a similar advantage can be obtained in the case that the capacitor dielectric film is formed of at least one material selected from the group consisting of HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1).
In addition, when the thin film capacitor of the second embodiment is formed in a semiconductor device having a transistor in which a refractory metal silicide is provided in a gate electrode and source/drain diffused layer regions, the anneal condition is required at a temperature which is not lower than the ZrO2 deposition temperature in the ALD process but which is not higher than a temperature where no aggregation of the refractory metal silicide occurs in the gate electrode and the source/drain diffused layer regions. The aggregation of the silicide is remarkable in a region having a small area, namely, in the gate electrode rather than the source/drain diffused layer regions. For example, in the device on the generation of the gate length 0.15 micron, the aggregation temperature is about 600 degrees Celsius. In this case, the anneal temperature is not lower than the ZrO2 deposition temperature in the ALD process but not higher than 600 degrees Celsius.
Now, a third embodiment of the present invention will be described.
According to this third embodiment, in a stacked MIM (metal-insulator-metal) capacitor in a DRAM or a logic mixed DRAM having a logic section and a memory section formed on the same chip, a lower electrode, a capacitor dielectric film and an upper electrode are sequentially formed in the ALD process by use of an ALD apparatus.
First, a conventional method for forming the stacked MIM capacitor in a DRAM or a logic mixed DRAM will be described. As shown in
In this conventional method for forming the stacked MIM capacitor, when the lower electrode is selectively removed, it is necessary to charge the resist 14 into the opening so as to prevent a portion which will become the lower electrode of the capacitor, from the etching. For the purpose of removing this resist, it is possible to remove this resist by using acid, in a MIS (metal-insulator-silicon) capacitor having the lower electrode formed of polysilicon. However, in the MIM capacitor having the lower electrode formed of a metal such as TiN, it is impossible to remove this resist by using acid (SPM (sulfuric acid—peroxide mixture). Therefore, the resist is removed by a plasma removal processing plus an organic removal processing. However, this removal method is difficult to completely remove depositions which were generated in the etching and a removal residue of the resist.
Furthermore, in conventional method for forming the stacked MIM capacitor, it is difficult to avoid a plasma damage to the surface of the lower electrode when the lower electrode is selectively removed and when the resist is removed. In addition, since impurity such as carbon in atmosphere of a clean room deposits on the surface of the lower electrode, it is also difficult to maintain a boundary between the lower electrode and the capacitor dielectric film in a good condition, with the result that the characteristics of the capacitor dielectric film is deteriorated.
In the third embodiment of the present invention, on the other hand, in a thin film capacitor of a MIM structure in which each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru, and a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), the lower electrode, the capacitor dielectric film and the upper electrode are sequentially formed in the same machine in the ALD process by using an ALD apparatus. With this arrangement, a boundary between the lower electrode and the capacitor dielectric film can be maintained in a good condition.
Now, a method in accordance with the third embodiment of the present invention for forming the stacked MIM capacitor in the DRAM or the logic mixed DRAM, will be described with reference to diagrammatic sectional views of
First, as shown in
Then, as shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
Here, referring to
For formation of the TiN film, TiCl4 and NH3 are used as a starting material gas. A film deposition temperature is on the order of 300 to 500 degrees Celsius.
First, TiCl4 is supplied to a chamber of the ALD apparatus. Thus, only a one-atom layer is deposited, by reaction, on a surface of the interlayer insulator film 32 including the surface of the cylinder formed in the interlayer insulator film 32. Next, the supply of TiCl4 is stopped, and a purge gas is introduced into the chamber so that an excessive unreacted TiCl4 is removed.
Thereafter, NH3 is supplied to replace a Cl group which terminates Ti grown on the surface of the interlayer insulator film, with a NH2 group. In this process, HCl is produced as a reaction subproduct. Then, the supply of NH3 is stopped, and the inert gas represented by Ar or N2 is introduced into the chamber as the purge gas so that an unreacted NH3 and the reaction subproduct HCl are removed.
Then, TiCl4 is supplied again so that only another one-atom layer is deposited. The supply of TiCl4 is stopped, and the purge gas in introduced so that an unreacted TiCl4 and the reaction subproduct HCl are removed. The supply of the purge gas is stopped, and NH3 is supplied.
In this manner, a cycle of the TiCl4 supply, the purge, the NH3 supply and the purge sequentially carried in the named order, is repeated necessary times, until the lower electrode metal film 34 of TiN having the film thickness of 5 to 50 nm is obtained.
Thereafter, similarly to the procedure of the formation of the ZrO2 thin film in the first embodiment as shown in
Furthermore, the upper electrode metal film 36a of TiN having the film thickness of 5 to 50 nm is formed on the capacitor dielectric film 35 by alternately supplying TiCl4 and NH3, similarly to the procedure of the formation of the lower electrode metal film 34 as shown in
In the example shown in
This can be applied to the lower electrode 34. Namely, it is not necessary to form the whole of the lower electrode 34 by use of the ALD process. The lower electrode 34 can be formed first by the sputtering, for example, and then, only a portion of the lower electrode 34 corresponding to the boundary layer is formed by the ALD process, and thereafter, the capacitor dielectric film 35 and the upper electrode 36a are succeedingly formed by the ALD process.
In other words, the lower electrode 34 and the upper electrode 36a are sufficient if only a boundary portion to the capacitor dielectric film 35 is formed by the ALD process. Therefore, it is sufficient if the film thickness of each of the lower electrode 34 and the upper electrode 36a to be formed by the ALD process has at least one-atom layer thickness. Accordingly, only a boundary portion to the capacitor dielectric film 35, of each of the lower electrode 34 and the upper electrode 36a, is formed by the ALD process to have at least one-atom layer thickness, and the other portion of each of the lower electrode 34 and the upper electrode 36a can be formed by use of the CVD process or the sputtering so that the whole film thickness of each of the lower electrode 34 and the upper electrode 36a becomes 5 to 50 nm.
Thereafter, as shown in
Succeedingly, as shown in
As shown in
As shown in
Furthermore, as shown in
In this third embodiment, since the lower electrode, the capacitor dielectric film and the upper electrode are continuously formed in the same machine (the same chamber) by use of the ALD apparatus which can control the composition of the film with an atom-layer level, it is possible to perfectly prevent the chemical and physical damages to the surface of the lower electrode, which would otherwise occur when the lower electrode is patterned and when the resist is removed. In addition, it is also possible to minimize deposition of carbons included in the air within the clean room, to the surface of the lower electrode and the surface of the capacitor dielectric film. Because of these reasons, it is possible to maintain a boundary between the lower electrode and the capacitor dielectric film and a boundary between the capacitor dielectric film and the upper electrode in a good condition. Furthermore, since the boundary between the lower electrode and the capacitor dielectric film is maintained in the good condition, it is possible to minimize the capacitance drop and the increase of the capacitor dielectric film leakage current.
In addition, after the MIM structure capacitor is formed, if the anneal is carried out similarly to the capacitor of the second embodiment, it is possible to realize a capacitor having a further large capacitance and a small leakage current. In this case, the anneal is carried out at a temperature which is not lower than the ZrO2 forming temperature in the ALD process but which is not higher than a temperature where no aggregation of a refractory metal silicide occurs in a gate electrode and source/drain diffused layer regions in the case that the refractory metal silicide is provided in the gate electrode and the source/drain diffused layer regions.
The present invention is in now way limited to the cylinder type capacitor, but can be applied to a planar capacitor and a box type capacitor.
Referring to
A bit contact 56 is formed in the interlayer insulator film 55 to reach one of each pair of source/drain diffused regions 54. A bit line 57 is formed on the interlayer insulator film 55 to be electrically connected to the bit contact 56. Furthermore, an interlayer insulator film 58 is deposited to cover the bit line 57 and the interlayer insulator film 55.
On the interlayer insulator film 58, a lower electrode 59 formed of a metal of a metal nitride, a capacitor dielectric film 60 formed of ZrO2, and an upper electrode 61 formed of a metal of a metal nitride, are continuously formed in the named order by the ALD apparatus. The lower electrode 59 is electrically connected to a capacitor contact 62 formed through the interlayer insulator films 58 and 55 to reach the other of each pair of source/drain diffused regions 54. A side wall 66 is formed on a side surface of each planar capacitor thus formed which is composed of the lower electrode 59, the capacitor dielectric film 60 and the upper electrode 61.
A common interconnection layer 63 is formed on the upper electrode 61 of each planar capacitor to interconnect the upper electrode 61 of the planar capacitors. An interlayer insulator film 64 is formed to cover the common interconnection layer 63, and a first metal layer 65 is formed on the interlayer insulator film 64 to constitute a first level metal interconnection.
Referring to
A bit contact 76 is formed in the interlayer insulator film 75 to reach one of each pair of source/drain diffused regions 74. A bit line 77 is formed on the interlayer insulator film 75 to be electrically connected to the bit contact 76. Furthermore, an interlayer insulator film 78 is deposited to cover the bit line 77 and the interlayer insulator film 75. A capacitor contact 82 is formed through the interlayer insulator films 78 and 75 to reach the other of each pair of source/drain diffused regions 74.
On the capacitor contact 82, a lower electrode 79a of W (tungsten) is formed. To cover the lower electrode 79a and the interlayer insulator film 78, a lower electrode 79b formed of a metal of a metal nitride, a capacitor dielectric film 80 formed of ZrO2, and an upper electrode 81 formed of a metal of a metal nitride, are continuously formed in the named order by the ALD apparatus. Thus, the box type capacitor is composed of the lower electrodes 79a and 79b, the capacitor dielectric film 80 and the upper electrode 81.
On the upper electrode 81, an insulator film 86 is formed to isolate the upper electrode 81 and the lower electrode 79 from each other. On the an insulator film 86, a common interconnection layer 83 is formed to interconnect the upper electrode 81b of the planar capacitors. An interlayer insulator film 84 is formed to cover the common interconnection layer 83, and a first metal layer 85 is formed on the interlayer insulator film 84 to constitute a first level metal interconnection.
Now, a fourth embodiment of the present invention will be described.
In this fourth embodiment, in a semiconductor device having a MIS thin film capacitor formed on an insulator film formed to over an uppermost interconnection layer, a capacitor dielectric film of the MIS thin film capacitor is formed by the ALD process which can carry out a film deposition at a low temperature and which makes the post-anneal in an oxidizing atmosphere unnecessary, and the MIS thin film capacitor is located to function as a decoupling capacitor for power supply lines.
Referring to
An interlayer insulator film 103 is formed to cover an uppermost interconnection (ground line) 101, another uppermost interconnection (power supply line) 102 and an underlying interlayer insulator film. On the interlayer insulator film 103, a lower electrode 105, a capacitor dielectric film 106 and an upper electrode 107 are formed in the named order to constitute a decoupling capacitor 104. The lower electrode 105 is connected through a contact 108 to the uppermost interconnection (ground line) 101, and the upper electrode 107 is connected through a contact 109 to the uppermost interconnection (power supply line) 102.
Now, a method for forming the decoupling capacitor shown in
In a logic device formed in a known fabricating process, on the interlayer insulator film 103, a lower electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the lower electrode 105 is formed at a position above the uppermost interconnection (ground line) 101 and is connected to the contact 108 reaching the uppermost interconnection (ground line) 101.
Thereafter, a capacitor dielectric film is deposited to cover the lower electrode 105 by use of the ALD process at a film deposition temperature of 200 to 400 degrees Celsius. This capacitor dielectric film is constituted of a single-layer film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), or alternatively, a multi-layer film formed of at least two materials selected from the group mentioned above. Then, the capacitor dielectric film is patterned into a desired shape to form the capacitor dielectric film 106.
Then, to cover the capacitor dielectric film 106, an upper electrode film is formed of at least one material selected from the group consisting of TiN, Ti, TaN, Ta, W, WN, Pt, Ir, Ru, by means of a sputtering process or a ALD process, and then, is patterned into a desired shape, so that the upper electrode 107 is formed to partially cover the capacitor dielectric film 106 and is connected to the contact 109 reaching the uppermost interconnection (power supply line) 102. Thus, the thin film capacitor functioning as the decoupling capacitor is formed in the semiconductor device.
In the embodiment shown in
In addition, in the embodiment shown in
As mentioned above, in the fourth embodiment, since a capacitor dielectric film having a high dielectric constant is formed by the ALD process which can carry out a film deposition at a low temperature and which makes the post-anneal in an oxidizing atmosphere unnecessary, the thin film capacitor can be formed in the semiconductor device with no characteristics deterioration attributable to oxidation of the interconnection layer and with no drop in yield of production.
Incorporation of the thin film capacitor in accordance with the present invention into the semiconductor device as the decoupling capacitor can overcome the problem mentioned hereinbefore of the conventional on-chip decoupling capacitor and can simultaneously realize a low inductance and a large capacitance which are advantages of the on-chip decoupling capacitor.
As mentioned above, in the MIM thin film capacitor in accordance with the present invention, since a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), it is possible to reduce a leakage current and to increase a capacitance value.
Furthermore, in the MIM thin film capacitor in accordance with the present invention, since an anneal is carried out after a capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<X<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1−z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), it is possible to further reduce a leakage current and to further increase a capacitance value.
In the stacked MIM thin film capacitor in accordance with the present invention provided in a DRAM or a logic mixed DRAM, since a lower electrode, a capacitor dielectric film and an upper electrode are continuously formed in the ALD process, a silicide layer formed in a gate electrode and a source/drain diffused region is never deteriorated, and a sufficient capacitance value (a maximum capacitance value per a unitary area and a minimum leakage current value per a unitary area) can be ensured as a capacitor of each DRAM cell provided in a memory section.
Moreover, according to the present invention, since a thin film capacitor having a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<Y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), is formed over an uppermost interconnection layer in a semiconductor device, it is possible to realize a low-inductance, large-capacitance, one-chip decoupling capacitor, which meets with a speedup of an LSI.
The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.
Claims
1-14. (Cancelled).
15. A method for fabricating a semiconductor device, comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on the capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode, wherein at a stage after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature not lower than a film deposition temperature in the atomic layer deposition.
16. A method for fabricating a semiconductor device including a transistor having a gate electrode and source/drain diffused layers having a silicide of a refractory metal, the method comprising the steps of forming a lower electrode of a capacitor, forming on the lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and, forming an upper electrode of said capacitor on said capacitor dielectric film, so that the capacitor is constituted of said lower electrode, said capacitor dielectric film and said upper electrode.
17. A method claimed in claim 16 wherein after formation of said capacitor dielectric film, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.
18. A method claimed in claim 16 wherein after formation of said upper electrode, a heat treatment is carried out at a temperature which is not lower than a film deposition temperature in the atomic layer deposition but which is not higher than a temperature where no aggregation of said silicide of refractory metal occurs in said gate electrode and said source/drain diffused layers.
19. A method claimed in claim 16 wherein said capacitor constitutes a cell capacitor of each DRAM cell and wherein said lower electrode, said capacitor dielectric film and said upper electrode are continuously deposited in the same machine.
20. A method claimed in claim 16 wherein said cell capacitor of each DRAM cell is of a cylinder type, and wherein after the formation of said upper electrode, said lower electrode, said capacitor dielectric film and said upper electrode, which are positioned in an upper portion of the cylinder, are removed so that a cylinder type capacitor is formed, and said upper electrode charged into an inside of the cylinder is connected to a common interconnection.
21. A method for fabricating a semiconductor device having a capacitor of a MIM (metal-insulator-metal) structure formed on an insulator film formed on an interconnection layer, the method comprising the steps of forming a lower electrode of the capacitor, forming on said lower electrode, by means of an atomic layer deposition, a capacitor dielectric film formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and then, forming an upper electrode on said capacitor dielectric film.
22. A method of fabricating a semiconductor device comprising forming source and drain regions of a transistor, forming a metal plug in contact with one of the source and drain regions of said transistor, forming a lower metal electrode of a capacitor in contact with said metal plug, forming a capacitor dielectric film on said lower metal electrode by atomic layer deposition (ALD), and forming an upper metal electrode on said capacitor dielectric film, said capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1) and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and said capacitor dielectric film having a film thickness of 5 to 15 nm,
- whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature irrespective of a thinner dielectric film thickness.
23. The method as claimed in claim 22, wherein said upper electrode is formed by atomic layer deposition (ALD).
24. The method as claimed in claim 23, wherein said lower electrode is formed by atomic layer deposition (ALD).
25. A method of fabricating a semiconductor device comprising forming first and second diffusion regions of a transistor selectively in a semiconductor substrate, forming first and second metal silicide layers on respective surface portions of said first and second diffusion regions, covering said semiconductor substrate and said transistor with a first insulating layer, forming first and second holes in said first insulating layer to expose respective parts of said first and second metal silicide layers, filling said first and second holes with first and second metal plugs respectively, forming a bit line formed over said first insulating layer in contract with said first metal plug, forming a second insulating layer formed over said first insulating layer and said bit line, forming a third contact hole in said second insulating layer, filling said third hole with a third metal plug, and forming a lower metal electrode of a capacitor in contact with said third metal plug, forming a dielectric film on said lower metal electrode by atomic layer deposition (ALD), said dielectric film being made of a dielectric material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), and (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), and forming an upper metal electrode on said dielectric film, whereby said semiconductor device results in a better electrical connection between said capacitor and said transistor without aggregation of said first and second metal silicide layers occurring and in suppressing a change in leakage current between said lower metal electrode and said upper metal electrode of said capacitor against a change in temperature.
26. The method as claimed in claim 25, wherein said upper electrode is formed by atomic layer deposition (ALD).
27. The method as claimed in claim 26, wherein said lower electrode is formed by atomic layer deposition (ALD).
Type: Application
Filed: Oct 18, 2004
Publication Date: Mar 10, 2005
Inventors: Toshihiro Iizuka (Tokyo), Tomoe Yamamoto (Tokyo), Mami Toda (Tokyo), Shintaro Yamamichi (Tokyo)
Application Number: 10/967,436