Patents by Inventor Mamoru Furuta
Mamoru Furuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7993964Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.Type: GrantFiled: July 27, 2009Date of Patent: August 9, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Patent number: 7981734Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.Type: GrantFiled: July 8, 2009Date of Patent: July 19, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
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Patent number: 7977169Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.Type: GrantFiled: February 9, 2007Date of Patent: July 12, 2011Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu
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Publication number: 20090286351Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi HIRAO, Takahiro HIRAMATSU, Mamoru FURUTA, Hiroshi FURUTA, Tokiyoshi MATSUDA
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Publication number: 20090269881Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.Type: ApplicationFiled: July 8, 2009Publication date: October 29, 2009Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru FURUTA, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
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Patent number: 7598520Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.Type: GrantFiled: June 1, 2007Date of Patent: October 6, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Thin film transistor including low resistance conductive thin films and manufacturing method thereof
Patent number: 7576394Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.Type: GrantFiled: February 1, 2007Date of Patent: August 18, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida -
Publication number: 20070278490Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.Type: ApplicationFiled: June 1, 2007Publication date: December 6, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Thin film transistor including low resistance conductive thin films and manufacturing method thereof
Publication number: 20070187760Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.Type: ApplicationFiled: February 1, 2007Publication date: August 16, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida -
Publication number: 20070187678Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.Type: ApplicationFiled: February 9, 2007Publication date: August 16, 2007Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu
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Patent number: 7173681Abstract: In an electrode substrate used in a liquid crystal display device, a contact hole for connecting a signal line to a drain electrode of a pixel thin film transistor is provided in a position overlapping a pixel electrode in order to improve yields by reducing a short circuit between adjacent pixel electrodes. With this configuration, the contact hole does not exist at a boundary between the two adjacent pixel electrodes. Accordingly, the pixel electrodes do not suffer an influence of an electrode material remaining at a recess of the contact hole, and a short circuit between the adjacent pixel electrodes can be thereby prevented.Type: GrantFiled: February 4, 2004Date of Patent: February 6, 2007Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Hideyuki Takahashi, Kohei Nagayama, Mamoru Furuta, Shinichi Kawamura, Toshihiro Ninomiya, Koji Soma
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Publication number: 20060267015Abstract: A gate electrode of a thin film transistor is composed by a three layer structure obtained by laminating a titanium nitride layer as an upper layer on an aluminum layer as a base layer and by laminating an unalloyed titanium layer as a lower layer under the base layer. An ion implantation is used as an ion doping into a source region and drain region as an active layer of the thin film transistor. The source region and the drain region are annealed at a low temperature of 350° C. to 450° C. to be activated. A chemical reaction between the base layer and the upper layer and between the base layer and the lower layer can be suppressed. The rise of the resistance value in the gate electrode can be suppressed. The resistance of the gate electrode can be reduced. The fluctuation of the threshold voltage of the thin film transistor can be suppressed.Type: ApplicationFiled: April 26, 2006Publication date: November 30, 2006Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Hiroshi Omi, Mamoru Furuta, Shoso Nambu, Takayoshi Dohi, Akihiro Takami, Shuji Manda, Hajime Inoue
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Publication number: 20040160543Abstract: In an electrode substrate used in a liquid crystal display device, a contact hole for connecting a signal line to a drain electrode of a pixel thin film transistor is provided in a position overlapping a pixel electrode in order to improve yields by reducing a short circuit between adjacent pixel electrodes. With this configuration, the contact hole does not exist at a boundary between the two adjacent pixel electrodes. Accordingly, the pixel electrodes do not suffer an influence of an electrode material remaining at a recess of the contact hole, and a short circuit between the adjacent pixel electrodes can be thereby prevented.Type: ApplicationFiled: February 4, 2004Publication date: August 19, 2004Applicant: TOSHIBA MATSUSHITA DISPLAY TECHNOLOGY CO., LTD.Inventors: Hideyuki Takahashi, Kohei Nagayama, Mamoru Furuta, Shinichi Kawamura, Toshihiro Ninomiya, Koji Soma
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Patent number: 6420760Abstract: A first insulation film is formed as a gate insulation film of a thin film transistor, and a gate electrode is formed on the gate insulation film. Then, dopant is implanted to form source and drain regions. A second insulation film having refractive index n1 and film thickness d2 is formed to cover the first insulation film and gate electrode as an interlayer insulation film. After forming the second insulation film, laser with wavelength &lgr; is applied to activate the dopant. The film thicknesses d1 and d2 of the first and second insulation films satisfy conditions against the laser wavelength &lgr; for forming a reflection protective film at regions where activation is necessary. At the same time, the film thicknesses d1 and d2 are set in a way that the interlayer insulation film on the gate electrode forms a reflective film. This reduces the thermal damage to the gate electrode from the laser during dopant activation.Type: GrantFiled: August 29, 2001Date of Patent: July 16, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mamoru Furuta, Koji Soma
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Publication number: 20020004260Abstract: A first insulation film is formed as a gate insulation film of a thin film transistor, and a gate electrode is formed on the gate insulation film. Then, dopant is implanted to form source and drain regions. A second insulation film having refractive index n1 and film thickness d2 is formed to cover the first insulation film and gate electrode as an interlayer insulation film. After forming the second insulation film, laser with wavelength &lgr; is applied to activate the dopant. The film thicknesses d1 and d2 of the first and second insulation films satisfy conditions against the laser wavelength &lgr; for forming a reflection protective film at regions where activation is necessary. At the same time, the film thicknesses d1 and d2 are set in a way that the interlayer insulation film on the gate electrode forms a reflective film. This reduces the thermal damage to the gate electrode from the laser during dopant activation.Type: ApplicationFiled: August 29, 2001Publication date: January 10, 2002Inventors: Mamoru Furuta, Koji Soma
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Patent number: 6309917Abstract: A first insulation film is formed as a gate insulation film of a thin film transistor, and a gate electrode is formed on the gate insulation film. Then, dopant is implanted to form source and drain regions. A second insulation film having refractive index n1 and film thickness d2 is formed to cover the first insulation film and gate electrode as an interlayer insulation film. After forming the second insulation film, laser with wavelength &lgr; is applied to activate the dopant. The film thicknesses d1 and d2 of the first and second insulation films satisfy conditions against the laser wavelength &lgr; for forming a reflection protective film at regions where activation is necessary. At the same time, the film thicknesses d1 and d2 are set in a way that the interlayer insulation film on the gate electrode forms a reflective film. This reduces the thermal damage to the gate electrode from the laser during dopant activation.Type: GrantFiled: May 9, 2000Date of Patent: October 30, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mamoru Furuta, Koji Soma
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Patent number: 6034748Abstract: With a conventional thin film transistor comprising a plurality of series-connected thin film transistors each having a plurality of LDD structures, leakage current can be decreased to a large effect but the area of an element can hardly be reduced. By connecting gate electrodes (15) of a plurality of thin film transistors only with an implanted region (13b) which is formed by implanting an impurity at a low concentration into a semiconductor thin film employed as an active layer, both reduction in element size and decrease in leakage current can be realized.Type: GrantFiled: April 2, 1998Date of Patent: March 7, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Mamoru Furuta
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Patent number: 5766989Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.Type: GrantFiled: December 27, 1995Date of Patent: June 16, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeki Maegawa, Mamoru Furuta, Hiroshi Tsutsu, Tetsuya Kawamura, Yutaka Miyata
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Patent number: 5680190Abstract: A liquid crystal display apparatus includes: a liquid crystal layer; a first substrate and a second substrate interposing the liquid crystal layer therebetween; a pixel electrode and a counter electrode respectively provided on opposing faces of the first substrate and the second substrate for applying a voltage to the liquid crystal layer; and a thin-film transistor provided on the first substrate and electrically connected to the pixel electrode, the thin-film transistor including a semiconductor layer having a source region and a drain region, wherein the pixel electrode is divided into a first sub-pixel electrode and a second sub-pixel electrode; parts of the first and second sub-pixel electrodes are overlapped via an insulating layer with each other; and at least one of the first and second sub-pixel electrodes is made of the same transparent material as a material for the semiconductor layer.Type: GrantFiled: June 1, 1995Date of Patent: October 21, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akiko Michibayashi, Tetsuya Kawamura, Mamoru Furuta, Yutaka Miyata
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Patent number: 5591668Abstract: A laser annealing method for a semiconductor thin film for irradiating the semiconductor thin film with a laser beam having a section whose outline includes a straight-line portion, so as to change the crystallinity of the semiconductor thin film is provided, wherein the semiconductor thin film is overlap-irradiated with the laser beam while the laser beam is shifted in a direction different from a direction along the straight-line portion. A thin film semiconductor device fabricated by use of the laser annealing method is also provided.Type: GrantFiled: March 13, 1995Date of Patent: January 7, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeki Maegawa, Tetsuya Kawamura, Mamoru Furuta, Yutaka Miyata