Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.

Abstract: In certain aspects, a memory device includes a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The plurality of memory cells includes a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state. The control circuit is configured to perform a first program pass on the first set of memory cells. The control circuit is configured to continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages. A threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell. The control circuit is configured to perform a second program pass on the first set of memory cells.

Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Abstract: A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.

Abstract: A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.

Abstract: A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level.

Abstract: A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Abstract: In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

Abstract: When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

Abstract: In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells.

Abstract: Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.