Abstract: A HC adsorption type three-way catalytic converter is arranged in an exhaust gas passage of a diesel engine at a position upstream of a diesel particulate filter or a NOx trapping catalytic converter. Upon need of reactivation of the diesel particulate filter or NOx trapping catalytic converter under cold operation of the engine, a control unit carries out lowering an excess air ratio of the exhaust gas of the engine when the temperature of the catalyst bed of the three-way catalytic converter is lower than or equal to a first predetermined temperature (viz., oxidization activation temperature); raising the excess air ratio of the exhaust gas when the temperature of the catalyst bed of the three-way catalytic converter is higher than the first predetermined temperature but lower than or equal to a second predetermined temperature (viz.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.

Abstract: A semiconductor device includes a first pad, a second pad, a first buffer and a second buffer. The first pad is connected to another semiconductor device in a multi-chip package, and the second pad makes a probing connection in a wafer test. The first buffer drives the another semiconductor device connected to the first pad. The second buffer, being driven by the first buffer, drives a load capacitance of a tester connected to the second pad with the driving power greater than the driving power of the first buffer, and has its active/inactive state controlled by a control signal. The semiconductor device can provide the driving power necessary for the wafer test, and drive the another semiconductor device with preventing generation of drive noise and suppressing current consumption in the normal operation of the multi-chip package.

Abstract: A method of controlling an internal combustion engine for warm-up of catalyst of an exhaust gas treatment device is disclosed. The method comprises generating a warm-up demand for heating the catalyst subject to constraint on stable combustion. Based on the warm-up demand, a reduction in excess air ratio is determined. A desired value in excess air ratio is modified by the reduction to provide a modified desired value in excess air ratio. Based on the reduction, a desired value in EGR rate is modified to provide a modified desired value in EGR rate. Based on the modified desired value in EGR rate, an EGR command signal is determined.

Abstract: A diesel particulate filter 14 that traps particulate matters in an exhaust gas and a NOx trap catalyst 13 that traps NOx in the exhaust gas are disposed in an exhaust passage (10) in an internal combustion engine (1). When a regeneration timing of the diesel particulate filter (14) and one of a regeneration timing of SOx and a regeneration timing of NOx are overlapped, the diesel particulate filter regeneration is carried out first and thereafter, the SOx regeneration or the NOx regeneration is carried out.

Abstract: An intake air control system for an internal combustion engine is provided which comprises an intake throttle valve that controls an intake air quantity of air flowing into the engine, an EGR valve that controls a quantity of exhaust gas recirculated back to a portion of an intake system of the engine downstream of the intake throttle valve, and a control unit that controls the intake throttle valve and the EGR valve in accordance with an operating condition of the engine. The control unit includes a target opening area calculating section that calculates a target opening area of the intake throttle valve based on a target EGR ratio corresponding to the operating condition of the engine, and a control section that controls an opening degree of the intake throttle valve based on the target opening area. An intake air control method is also provided.

Abstract: A HC adsorption type three-way catalytic converter is arranged in an exhaust gas passage of a diesel engine at a position upstream of a diesel particulate filter or a NOx trapping catalytic converter. Upon need of reactivation of the diesel particulate filter or NOx trapping catalytic converter under cold operation of the engine, a control unit carries out lowering an excess air ratio of the exhaust gas of the engine when the temperature of the catalyst bed of the three-way catalytic converter is lower than or equal to a first predetermined temperature (viz., oxidization activation temperature); raising the excess air ratio of the exhaust gas when the temperature of the catalyst bed of the three-way catalytic converter is higher than the first predetermined temperature but lower than or equal to a second predetermined temperature (viz.

Abstract: A line delay generator including a packetizing circuit, one port RAM and a RAM controller. The RAM controller provides the one port RAM with a write command to write packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM, and output them as line delay data. The line delay generator can solve a problem involved in a conventional line delay generator in that because m (positive integer) two-port FIFOs must be connected in cascade to generate m line delay data, the FIFO memory becomes bulky.

Abstract: When an air excess rate is controlled to be reduced based upon an early activation demand of an exhaust gas purification apparatus or a regeneration demand of NOx trap catalyst at a state immediately after an engine has started from at a cold condition, a fuel injection state (injection timing of a main injection, a pilot injection quantity, an injection pressure and so on) from a fuel injection valve is variably controlled so that a crank angle position where a heat generation rate is maximized is kept constant, thereby stabilizing a combustion and preventing combustion fluctuations.

Abstract: In a cold condition before a warming-up completion in a diesel engine, when an engine power is less than a predetermined value, an air excess rate is controlled to a second air excess rate being smaller than a target air excess rate set after the warming-up completion, thereby promoting a warming-up of an exhaust gas purification catalyst due to rise of an exhaust gas temperature, and when the engine power is more than the predetermined value, the air excess rate is controlled to a first air excess rate being larger than the target air excess rate, thereby decreasing HC emission quantity from a combustion chamber. Accordingly, a total emission quantity of HC at the clod condition is decreased.

Abstract: An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

Abstract: A semiconductor integrated circuit can variably set the driving power of all or part of internal input/output terminals and internal output terminals used within a multi-chip package. It can increase the driving power at an individual wafer test before packaging to sufficiently drive a load connected between a tester and the internal input/output terminals and internal output terminals, and can reduce the driving power after packaging. It can prevent noise and power consumption from being increased.

Abstract: An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

Abstract: An integrated circuit is provided that can achieve the unit test of its memory simply and positively. It makes a decision as to whether a memory is normal or not according to a 1-bit identity decision result output from an identity/nonidentity decision circuit. It obviates the need for assigning a plurality of decision terminals to each chip to be tested, making it possible to simultaneously test the same number of chips as the total number of the decision terminals of a tester, which is physically limited. It can improve test efficiency and reduce test cost.

Abstract: A fuel injection control system is arranged to decide the execution of a pilot fuel injection based on evaluation functions indicative of degree of a pilot fuel injection demand, to decide an engine operating condition, to calculate a fuel injection quantity for each cylinder when the engine operating condition is in the predetermined low-load operating region, to calculate a pilot fuel injection quantity for each cylinder by multiplying a predetermined ratio to the fuel injection quantity in the predetermined low-load operating region and when the pilot fuel injection is executed, and to calculate a main fuel injection quantity by subtracting the pilot fuel injection quantity from the fuel injection quantity. Therefore, this arrangement enables accurate decision as to the execution of the pilot fuel injection and proper control of pilot and main fuel injection quantities.

Abstract: A method for testing a semiconductor memory device according to one embodiment comprises the steps of: checking data in all addresses of the semiconductor memory device for correctness in-units of m×n bits: ending if it is determined that data in all the semiconductor memory device; if there is a defective address, comparing each m-bit data constituting the (m×n)-bit data corresponding to the defective address with its expected value; and if the comparison result indicates that the m-bit data is erroneous, determining whether the defective semiconductor memory device can be repaired. Due to this step, man hours required for testing a semiconductor memory device having a wide data bus of an (m×n)-bit width can be considerably reduced.

Abstract: A paper punching device is disposed on a paper conveyer passage for punching plural holes in a paper that passes on said paper conveyer passage, and comprises plural punches disposed on the upper side of said paper conveyer passage at right angles with the direction in which the paper is conveyed, plural pushing members mounted on the upper ends of said plural punches, and a punch-operating mechanism for operating said plural pushing mechanisms.

Abstract: An external clock signal is transmitted as a clock signal to a memory core through a first signal transmitting path. In response to activation of the clock signal CLK, memory core starts a read operation. Read data output from memory core is latched by a latch circuit. An external signal designating a latch timing is transmitted as a latch timing signal to the latch circuit through a second signal transmitting path. A delay circuit is provided in at least one of the first and second signal transmitting paths, so that the first and second signal transmitting paths come to have the same signal delay.

Abstract: In driving apparatus and method for a hybrid vehicle, a controller is provided and programmed: to calculate a target driving force [tFd], the target driving force representing a target value of a vehicular driving force; to calculate a basic target engine speed [tNinb] on the basis of tFd, the basic target engine speed representing a basic target value of the engine speed; to calculate a power generation request quantity [tWg], the power generation request quantity representing a power to be generated by the motor/generator; to calculate a basic target engine torque [tTeg] on the basis of tFd, tWg, and tNinb, the basic target engine torque representing an engine torque to be developed when an output required for a vehicular drive and for a power drive of the motor/generator is developed at tNinb; to calculate a limit torque [tTlim] during an occurrence of a power generation request on the basis of tNinb, this limit torque representing a limit torque of the eng