Abstract: An exhaust passage (2) of a diesel engine (1) is connected to an intake passage (3) via an exhaust gas recirculation passage (4) provided with an exhaust gas recirculation valve (6). A turbine (52) of a variable capacity turbocharger (50) is provided in the exhaust passage (2). The controller (41) controls the opening of the exhaust gas recirculation valve (6), and the opening of a nozzle (53) of the turbine (52). A controller (41) first calculates a target exhaust gas recirculation valve opening surface area based on a target exhaust gas recirculation flowrate, and controls the exhaust gas recirculation valve opening to the target exhaust gas recirculation valve opening surface area.

Abstract: A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.

Abstract: In order to enable enlargement/reduction of data with a simple structure in a first-in first-out memory device thereby reducing the circuit scale of this device, output terminals (Q.sub.0 to Q.sub.3) of a read clock counter (16) are shifted to low order digits and connected to input terminals (A.sub.0 to A.sub.2) of a read address decoder (18). The read clock counter (16) and a read data sense amplifier (19) operate in response to read clocks (RK2). Enlarged read data (RD) are outputted from the read data sense amplifier (19). It is possible to implement enlargement/reduction of data by changing connection between the read clock counter (16) and the read address decoder (18), thereby remarkably simplifying the circuit structure of the first-in first-out memory device having an enlargement/reduction function.