Patents by Inventor Manabu Yanagihara

Manabu Yanagihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210183747
    Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y ?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm ?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.
    Type: Application
    Filed: March 2, 2021
    Publication date: June 17, 2021
    Inventors: Hidekazu NAKAMURA, Manabu YANAGIHARA, Tomohiko NAKAMURA, Yusuke KATAGIRI, Katsumi OTANI, Takeshi KAWABATA
  • Patent number: 11031935
    Abstract: A switching circuit includes; a switching element; a driver; a diode connected between a source terminal and a gate terminal of the switching element; a resistor connected between the driver and the gate terminal of the switching element; a series circuit connected in parallel with the resistor, and including a capacitor and a resistor; and a diode including an anode on a side of the gate terminal of the switching element and a cathode on a side of a second output terminal of the driver. The diode is connected in parallel with at least the capacitor out of the capacitor and the resistor connected in series.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: June 8, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daijiro Arisawa, Takeshi Azuma, Daisuke Yamamoto, Yoshihisa Minami, Manabu Yanagihara
  • Publication number: 20200395933
    Abstract: A switching circuit includes; a switching element; a driver; a diode connected between a source terminal and a gate terminal of the switching element; a resistor connected between the driver and the gate terminal of the switching element; a series circuit connected in parallel with the resistor, and including a capacitor and a resistor; and a diode including an anode on a side of the gate terminal of the switching element and a cathode on a side of a second output terminal of the driver. The diode is connected in parallel with at least the capacitor out of the capacitor and the resistor connected in series.
    Type: Application
    Filed: August 26, 2020
    Publication date: December 17, 2020
    Inventors: Daijiro Arisawa, Takeshi AZUMA, Daisuke YAMAMOTO, Yoshihisa MINAMI, Manabu YANAGIHARA
  • Publication number: 20200144386
    Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 7, 2020
    Inventors: Yusuke Kanda, Hideyuki Okita, Manabu Yanagihara, Takeshi Harada
  • Publication number: 20200119178
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer disposed above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a third nitride semiconductor layer selectively disposed above the second nitride semiconductor layer and containing a p-type first impurity element; a high resistance region disposed in the third nitride semiconductor layer, the high resistance region containing a second impurity element and having a specific resistance higher than a specific resistance of the third nitride semiconductor layer; and a gate electrode disposed above the high resistance region, wherein an end of the high resistance region is inside a surface end of the third nitride semiconductor layer.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 16, 2020
    Inventors: Hideyuki OKITA, Manabu YANAGIHARA, Masahiro HIKITA
  • Publication number: 20200105917
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer having a greater band gap than the first nitride semiconductor layer; a source electrode and a drain electrode on the second nitride semiconductor layer apart from each other; a third nitride semiconductor layer, between the source electrode and the drain electrode, containing a p-type first impurity and serving as a gate; and a fourth nitride semiconductor layer, between the third nitride semiconductor layer and the drain electrode, containing a p-type second impurity, wherein the average carrier concentration of the fourth nitride semiconductor layer is lower than the average carrier concentration of the third nitride semiconductor layer.
    Type: Application
    Filed: September 18, 2019
    Publication date: April 2, 2020
    Inventors: Hideyuki OKITA, Manabu YANAGIHARA, Takahiro SATO, Masahiro HIKITA
  • Patent number: 10475802
    Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than a band gap of the first nitride semiconductor layer; a first active region which includes a source electrode, a drain electrode, and a gate electrode, and has a first carrier layer located in the first nitride semiconductor layer; and a second active region which is on an extension of a long-side direction of the drain electrode and has a second carrier layer located in the first nitride semiconductor layer via an element isolation region, and a potential of the second carrier layer is substantially same as a potential of a source extraction electrode in the second active region or is an intermediate potential between a potential of a gate extraction electrode and the potential of the source extraction electrode opposite a short side of the drain electrode.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ayanori Ikoshi, Manabu Yanagihara
  • Publication number: 20190221503
    Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Hidekazu NAKAMURA, Manabu YANAGIHARA, Tomohiko NAKAMURA, Yusuke KATAGIRI, Katsumi OTANI, Takeshi KAWABATA
  • Patent number: 10312339
    Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: June 4, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Saichirou Kaneko, Hiroto Yamagiwa, Ayanori Ikoshi, Masayuki Kuroda, Manabu Yanagihara, Kenichiro Tanaka, Tetsuyuki Fukushima
  • Patent number: 10090220
    Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 2, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ayanori Ikoshi, Masahiro Hikita, Keiichi Matsunaga, Takahiro Sato, Manabu Yanagihara
  • Patent number: 10083870
    Abstract: A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a second electrode; a first field-effect transistor including a third gate electrode, a third electrode, and a fourth electrode; and a second field-effect transistor including a fourth gate electrode, a fifth electrode, and a sixth electrode. The first electrode is electrically connected to the third gate electrode, the first gate electrode is electrically connected to the third electrode, the second electrode is electrically connected to the fourth gate electrode, the second gate electrode is electrically connected to the fifth electrode, and the fourth electrode is electrically connected to the sixth electrode.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 25, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Ohori, Ayanori Ikoshi, Hiroto Yamagiwa, Manabu Yanagihara
  • Publication number: 20180211878
    Abstract: A semiconductor device includes: a first bidirectional switch element including a first gate electrode, a second gate electrode, a first electrode, and a second electrode; a first field-effect transistor including a third gate electrode, a third electrode, and a fourth electrode; and a second field-effect transistor including a fourth gate electrode, a fifth electrode, and a sixth electrode. The first electrode is electrically connected to the third gate electrode, the first gate electrode is electrically connected to the third electrode, the second electrode is electrically connected to the fourth gate electrode, the second gate electrode is electrically connected to the fifth electrode, and the fourth electrode is electrically connected to the sixth electrode.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Takahiro OHORI, Ayanori IKOSHI, Hiroto YAMAGIWA, Manabu YANAGIHARA
  • Publication number: 20180102426
    Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than a band gap of the first nitride semiconductor layer; a first active region which includes a source electrode, a drain electrode, and a gate electrode, and has a first carrier layer located in the first nitride semiconductor layer; and a second active region which is on an extension of a long-side direction of the drain electrode and has a second carrier layer located in the first nitride semiconductor layer via an element isolation region, and a potential of the second carrier layer is substantially same as a potential of a source extraction electrode in the second active region or is an intermediate potential between a potential of a gate extraction electrode and the potential of the source extraction electrode opposite a short side of the drain electrode.
    Type: Application
    Filed: November 14, 2017
    Publication date: April 12, 2018
    Inventors: Ayanori IKOSHI, Manabu YANAGIHARA
  • Patent number: 9923069
    Abstract: A nitride semiconductor device includes: a stacked structure portion having an active region; first and second main electrodes extending in a first direction; and a lead-out line (second lead-out line) electrically connected to the second main electrode and extends to one side in the first direction. The first main electrode has a first tip at an end which is on the side to which the lead-out line extends. The second main electrode has a second tip at an end which is on the side to which the lead-out line extends, and has, at a second tip-side in the first direction, a tapered portion having a width in a second direction which decreases with decreasing distance to the second tip. The lead-out line has a region projecting in the second direction from the tapered portion, and the first tip does not project further in the first direction than the second tip.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 20, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryusuke Kanomata, Ayanori Ikoshi, Hiroto Yamagiwa, Saichirou Kaneko, Manabu Yanagihara
  • Patent number: 9905563
    Abstract: A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 27, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Ohori, Chikashi Hayashi, Manabu Yanagihara
  • Publication number: 20180040706
    Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 8, 2018
    Inventors: Saichirou KANEKO, Hiroto YAMAGIWA, Ayanori IKOSHI, Masayuki KURODA, Manabu YANAGIHARA, Kenichiro TANAKA, Tetsuyuki FUKUSHIMA
  • Patent number: 9818835
    Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: November 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Saichirou Kaneko, Hiroto Yamagiwa, Ayanori Ikoshi, Masayuki Kuroda, Manabu Yanagihara, Kenichiro Tanaka, Tetsuyuki Fukushima
  • Patent number: 9761670
    Abstract: A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or InxGa1-xN (0<x?1) and formed on the substrate and a second semiconductor layer containing Al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 12, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Hikita, Manabu Yanagihara, Yasuhiro Uemoto
  • Patent number: 9680053
    Abstract: A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 13, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Kuroda, Manabu Yanagihara, Shinichi Oki
  • Publication number: 20170148701
    Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventors: Ayanori IKOSHI, Masahiro HIKITA, Keiichi MATSUNAGA, Takahiro SATO, Manabu YANAGIHARA