Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.

Abstract: A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.

Abstract: EMI noise is reduced and a component mounting area is suppressed, and downsizing of a power supply device is achieved. Power supply device includes transistor block, gate drive circuit block, and driver block. First gate terminal and second gate terminal are disposed on the same side as gate drive circuit block when viewed from a center of transistor block. Two output terminals are disposed on the same side as transistor block when viewed from a center of gate drive circuit block. At least a part of first drain terminal is included in a region sandwiched between first source terminal and second source terminal. Second drain terminal is disposed at a position deviating from an extension region that extends the region sandwiched between the first source terminal and the second source terminal beyond second source terminal as viewed from first drain terminal.

Abstract: The semiconductor device includes: a semiconductor substrate; a first transistor disposed above the semiconductor substrate and including a first source electrode, a first gate region, and a first drain electrode; and a second transistor disposed above the semiconductor substrate and including a second source electrode, a second gate region, and a second drain electrode. The first source electrode, the second gate region, and the second source electrode are substantially at an identical potential. The first drain electrode and the second drain electrode are substantially at an identical potential.

Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0?x?1, 0?y?1, 0?x+y?1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm?2.00×10?3×L2+0.173, tm being a thickness in mm and L being a length in mm.

Abstract: A nitride semiconductor device includes: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric layer that is formed on the electron supply layer; and an electrode that has a contact part which is in electrical contact with the electron supply layer via at least an opening passing through the dielectric layer. The contact part has: an inclined surface that is inclined so as to decrease in width toward the electron transit layer; a tip surface that is in contact with the bottom face of the opening; and a curved surface that is provided between the tip surface and the inclined surface and that is curved so as to protrude toward the electron transit layer.

Abstract: This semiconductor device includes first and second gate portions formed by a semiconductor layer containing acceptor impurities. First and second gate electrodes are arranged on parts of the first and second gate portions, respectively. The upper surface of the first gate portion includes a first side-space region located toward a source electrode and extending over length L1 and a second side-space region located toward a first drain electrode and extending over length L2. The upper surface of the second gate portion includes a third side-space region located toward the source electrode and extending over length L3 and a fourth side-space region located toward a second drain electrode and extending over length L4. The lengths L1 and L2 satisfy the relationship of L1>L2, and the lengths L3 and L4 satisfy the relationship of L3>L4.

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a first gate electrode, a source electrode, a drain electrode, and a second gate electrode. The second gate electrode is made of a material different from the first gate electrode. The first gate electrode and the second gate electrode are in contact with an upper surface of the gate layer. A second contact area, which is a contact area between the second gate electrode and the gate layer, is smaller than a first contact area, which is a contact area between the first gate electrode and the gate layer.

Abstract: A semiconductor device includes third active regions that connect two finger-end portions of field effect transistors (FETs) spaced apart from each other, and includes, above the third active regions, portions of a third nitride semiconductor layer that includes P-type impurities.

Abstract: An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.

Abstract: A semiconductor device includes a first semiconductor and a second semiconductor layer arranged thereon to generate a 2DEG in the first semiconductor layer. A source electrode and a drain electrode are arranged on the second semiconductor layer. A third semiconductor layer including an acceptor impurity is arranged on the second semiconductor layer between the source electrode and the drain electrode. A gate electrode is arranged on the third semiconductor layer. The second semiconductor layer defines a boundary between an element region including an FET and an element separation region. A guard ring is arranged on the second semiconductor layer in a peripheral part of the element region. The guard ring includes a fourth semiconductor layer arranged on the second semiconductor layer and including an acceptor impurity and a first electrode arranged on the fourth semiconductor layer and electrically connected to the source electrode or the 2GEG.

Abstract: The present disclosure provides a field effect transistor. The field effect transistor includes: an electron transport layer; an electron supply layer disposed on the electron transport layer; a plurality of source electrodes, a plurality of drain electrodes and a plurality of gate structures disposed on the electron supply layer. Each gate structure includes a gate layer and a gate electrode disposed on the gate layer. The field effect transistor further includes: a first high resistance region, a plurality of gate connection portions, a gate wiring and an insulating layer. The first high resistance region is disposed in the electron transport layer and the electron supply layer at a position between the drain electrodes adjacent to each other along an X direction. The gate connection portions electrically connect gate structures adjacent to each other along the X direction. The gate wiring is located above the first high resistance region.

Abstract: A nitride semiconductor epitaxial substrate includes: a Si substrate; a nitride semiconductor epitaxial layer disposed above the Si substrate; and a mixed crystal layer disposed between the Si substrate and the nitride semiconductor epitaxial layer, and containing Si and a group III metal element, the mixed crystal layer containing a high concentration of C. The mixed crystal layer has a concentration of at least 1.0×10+21 cm?3, and a transition metal element concentration of at most 5.0×10+16 cm?3.

Abstract: A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.

Abstract: A nitride semiconductor device includes a source electrode that is in contact with a second nitride semiconductor layer via a first opening portion and with which a portion is formed above a passivation film and a drain electrode that is in contact with the second nitride semiconductor layer via a second opening portion and with which a portion is formed above the passivation film such as to oppose the source electrode across a ridge portion, and the third nitride semiconductor layer has, between a ridge portion side end of the first opening portion and a first opening portion end of the ridge portion and/or between a ridge portion side end of the drain electrode and a second opening portion end of the ridge portion, an extension portion that extends outward from a portion below a thickness intermediate position of at least one side surface of the ridge portion.

Abstract: A nitride semiconductor device includes: a substrate; and a first nitride semiconductor layer, a second nitride semiconductor layer, and a third nitride semiconductor layer that are disposed above the substrate in the stated order. The first nitride semiconductor layer includes a recess. The second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer and is disposed in a region other than the recess. The third nitride semiconductor layer has a band gap larger than the band gap of the first nitride semiconductor layer and covers the first nitride semiconductor layer and the second nitride semiconductor layer including an inner wall of the recess. A contact angle at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ranges from 140° to less than 180°.

Abstract: A nitride semiconductor device includes: a substrate; a first semiconductor layer disposed above the substrate; a second semiconductor layer disposed above the first semiconductor layer; a third semiconductor layer disposed above the second semiconductor layer; a first opening which penetrates through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer; a semiconductor multilayer including a channel region; a fourth semiconductor layer disposed along the upper surface of the semiconductor multilayer; a gate electrode; a source electrode; a drain electrode; and a groove which is provided at an end portion of the nitride semiconductor device and penetrates through the second semiconductor layer to reach the first semiconductor layer, and a distance between the bottom of the first opening and the substrate is shorter than a distance between the bottom of the groove and the substrate.

Abstract: A semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; finger-shaped source electrodes on the second nitride semiconductor layer; finger-shaped drain electrodes disposed so as to be spaced apart from the source electrodes; and finger-shaped gate electrodes respectively disposed between the source electrodes and the drain electrodes. The gate electrodes are electrically connected, via a first gate integrated wiring, a plurality of second gate integrated wirings and a third gate integrated wiring, to gate pads located on one or both ends of the third gate integrated wiring. A plurality of source pads and the plurality of second gate integrated wirings are formed alternately in a first direction perpendicular to the longitudinal direction of the gate electrodes.

Abstract: A nitride semiconductor device includes: a first active area surrounded by an isolation area; and the following electrodes above the first active area: a source electrode; a first gate electrode and a second gate electrode, one on either side of and spaced from the source electrode in a first direction in plan view; and at least one drain electrode located in a direction opposite the source electrode relative to the first gate electrode or the second gate electrode. The source electrode, the first gate electrode, the second gate electrode, and the at least one drain electrode each include a finger-shaped portion extending in a second direction perpendicular to the first direction in the plan view. A first dielectric film is disposed above the source electrode. The first gate electrode and the second gate electrode are electrically connected by a gate electrode joiner disposed above the first dielectric film.

Abstract: EMI noise is reduced and a component mounting area is suppressed, and downsizing of a power supply device is achieved. Power supply device includes transistor block, gate drive circuit block, and driver block. First gate terminal and second gate terminal are disposed on the same side as gate drive circuit block when viewed from a center of transistor block. Two output terminals are disposed on the same side as transistor block when viewed from a center of gate drive circuit block. At least a part of first drain terminal is included in a region sandwiched between first source terminal and second source terminal. Second drain terminal is disposed at a position deviating from an extension region that extends the region sandwiched between the first source terminal and the second source terminal beyond second source terminal as viewed from first drain terminal.