Abstract: A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: Provided is a simulation method for simulating electrical properties of a bidirectional switch formed as a single element and having a double gate structure. A simulation is performed using an equivalent circuit having a symmetrical structure in which a drain electrode of a JFET and a drain electrode of another JFET are connected via a resistor.

Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

Abstract: A semiconductor device having: a substrate; a nitride semiconductor layer including a first semiconductor layer made of GaN or InxGa1-xN (0<x?1) and formed on the substrate and a second semiconductor layer containing Al and formed on the first semiconductor layer; and a protective film formed on the set of nitride semiconductor layers. The nitride semiconductor layer has an active section and an inactive section surrounding the active section, and a portion of the second semiconductor layer has been removed from the inactive section.

Abstract: A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.

Abstract: A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

Abstract: A two-wire AC switch suppressing heat from a bidirectional switch element inside the switch is provided. The two-wire AC switch 100a connected between an AC power supply 101 and a load 102 includes: a bidirectional switch element 103 which flows passing current bi-directionally, selects whether to flow or block the current, is connected in series with the AC power supply 101 and the load 102 to form a closed-loop circuit, and is made of a group-III nitride semiconductor; a full-wave rectifier 104 performing full-wave rectification on power supplied from the AC power supply 101; a power supply circuit 105 smoothing a voltage after the full-wave rectification to generate DC power; a first gate drive circuit 107 and a second gate drive circuit 108 each outputting a control signal to the bidirectional switch element 103; and a control circuit 106 controlling the first and second gate drive circuits 107 and 108.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: Provided is a simulation method for simulating electrical properties of a bidirectional switch formed as a single element and having a double gate structure. A simulation is performed using an equivalent circuit having a symmetrical structure in which a drain electrode of a JFET and a drain electrode of another JFET are connected via a resistor.

Abstract: A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

Abstract: A semiconductor device includes: a semiconductor chip; a protective film and an insulating film sequentially stacked over the semiconductor chip, and each having openings that expose source, drain, and gate pads; a heat dissipation terminal made of a material having a higher thermal conductivity than the insulating film; connection terminals formed on the source, drain, and gate pads and surrounded by the insulating film; and a mount substrate having connection pads. The semiconductor chip has a source electrode having a plurality of source fingers, a drain electrode having a plurality of drain fingers, and a gate electrode having a plurality of gate fingers. The source, drain, and gate pads are connected to the source electrode, the drain electrode, and the gate electrode, respectively. The connection terminals are respectively connected to the connection pads. The heat dissipation terminal is in close contact with the mount substrate.

Abstract: A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

Abstract: A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

Abstract: To provide a semiconductor equipment having high heat-transfer effect and breakdown voltage, and a method of manufacturing the same. The semiconductor equipment includes: a sealed container; a stem connected to the sealed container via a stem peripheral portion; and a semiconductor chip mounted on a top surface of the stem, inside the sealed container. The semiconductor chip is electrically connected to a lead provided to the stem, the stem peripheral portion, which is of a material that is different from the material of stem and the same as the material of the sealed container, is bonded along a periphery of the stem, and the sealed container is filled with a working fluid including at least one of ethanol, a perfluorocarbon, and a fluoroether.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.