Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Abstract: A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

Abstract: An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).

Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.

Abstract: Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Abstract: A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.

Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.

Abstract: A memory circuit includes one or several voltage generators for generating operating voltages for memory elements of the memory circuit and a means for selectively setting a current which may be supplied by one of the one or several voltage generators depending on an operating frequency for the memory circuit.

Abstract: The integrated chip according to the invention has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2-1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves for generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2-1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2-1.5).

Abstract: The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an on-chip signal. The contact region is imaged in a magnified fashion. An insertion device is provided that is suitable for providing a display of the on-chip signal in the imaging plane.

Abstract: Methods and apparatus for refreshing a dynamic memory cell in a memory circuit are provided, wherein the required time between refresh operations may be increased by increasing the potential difference between a high charge potential and common center potential used during a refresh mode relative to the potential difference between the high charge potential and the common center potential used during read or write modes.

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Abstract: A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

Abstract: An adapter apparatus for receiving memory modules, each of which has a plurality of data terminals and a plurality of control terminals, comprises first data terminals, first control terminals, a first socket for receiving a first memory module with second data terminals and second control terminals, wherein the second data terminals are associated to the data terminals of the first memory module, wherein the second control terminals are associated to the control terminals of the first memory module, a second socket for receiving a second memory module with third data terminals and third control terminals, wherein the third data terminals are associated to the data terminals of the second memory module, wherein the third control terminals are associated to the control terminals of the second memory module, a signal transformation circuit with an input and an output, wherein the input is connected to the first control terminals, and wherein the output is connected to the second control terminals and to the thi

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Abstract: An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.

Abstract: An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.

Abstract: A memory circuit includes one or several voltage generators for generating operating voltages for memory elements of the memory circuit and a means for selectively setting a current which may be supplied by one of the one or several voltage generators depending on an operating frequency for the memory circuit.

Abstract: The memory cells of a DRAM are refreshed such that the temporal sequence of the control signals for triggering the information refresh operation for the individual memory cells is set in accordance with the respective maximum retention time for the information in the memory cell.