Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

Abstract: The invention relates to an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.

Abstract: A method for structuring ferroelectric layers on semiconductor substrates retains or regenerates the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components. The addition of H2O or O2 results principally in the recovery of the electrostatic breakdown strength of the ferroelectric layer, which is of importance in particular when the ferroelectric serves as a dielectric of a storage capacitor and has to withstand electric fields of 5-10×106 V/m without a significant leakage current.

Abstract: The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode of a storage capacitor is insulated from the silicon substrate by a barrier layer. The barrier layer is patterned using a hard mask, in particular, made from SiO2, SiN, SiON, before the storage capacitor is applied, and the mask layer which remains after the patterning is removed so as to uncover the patterned barrier layer. The invention provides for the patterned barrier layer to be embedded in SiO2 by means of CVD (chemical vapor deposition) prior to the removal of the remaining mask layer, and for the remaining mask layer, together with the SiO2 embedding, to be removed from the surface of the barrier layer using an SiO2-CMP (chemical mechanical polishing) process.

Abstract: A method for structuring at least one layer to be structured. First, a mask is applied to the layer and the layer is structured using the mask. After the structuring step, the mask is then removed, while leaving behind redepositions of the material of the layer. The redepositions of the material of the layer are removed by mechanical polishing or chemical-mechanical polishing.

Abstract: The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode of a storage capacitor is insulated from the silicon substrate by a barrier layer. The barrier layer is patterned using a hard mask, in particular, made from SiO2, SiN, SiON, before the storage capacitor is applied, and the mask layer which remains after the patterning is removed so as to uncover the patterned barrier layer. The invention provides for the patterned barrier layer to be embedded in SiO2 by means of CVD (chemical vapor deposition) prior to the removal of the remaining mask layer, and for the remaining mask layer, together with the SiO2 embedding, to be removed from the surface of the barrier layer using an SiO2-CMP (chemical mechanical polishing) process.

Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

Abstract: A hard consumable mask is used which is consumed at a known rate during an etching process and is initially produced with a thickness such that the etching depth in the semiconductor material can be obtained as intended by comparing the etching rates of the material of the mask and of the semiconductor material to be etched.

Abstract: The invention relates, inter alia, to a method in which an electrically nonconductive mask layer (16) is applied to an electrically conductive contact layer which is supported by a substrate layer (12). A free space is made in the mask layer (16). Then, a plurality of layers (52 to 60) are electrochemically deposited in the free space. Then, layers (72 and 76) are applied above the layer (60) which was deposited last. Then, in a removal process, the mask layer (16) is removed down to the height of the top layer (76).

Abstract: A method for fabricating trenches for storage capacitors of DRAM semiconductor memories by plasma etching semiconductor substrates, includes fabricating a partial trench region with a cross-sectional profile deviating from essentially constant toward a larger cross-sectional profile. A surface of the partial trench region is passivated and the etching/passivating step is continued periodically, in order to fabricate further partial trench regions, until a predetermined overall trench depth has been reached.

Abstract: A method for etching an insulating layer of an electronic or microelectronic component uses a catalyst that is present during the etching. The method is in particular used for etching oxides. The catalyst may be added in a gaseous form and/or as an intermediate layer in the component. A component having structures etched in a dielectric material, in which traces of an etching catalyst are detectable in and/or around a contact hole and/or the structures is also provided.

Abstract: The method deals with plasma-structuring by etching, in particular with the plasma-structuring of materials at high temperatures. The application of a chemical etching process at high temperatures is made possible by the prior deposition of a polyimide mask.

Abstract: The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

Abstract: A method for structuring at least one layer to be structured. Initially, a mask is applied to the layer and the layer is structured using the mask. After the structuring step, the mask is then removed, while leaving behind redepositions of the material of the layer. The redepositions of the material of the layer are then removed by sound action.

Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.

Abstract: A layer is structured by first applying a sacrificial layer on the layer to be structured, forming a mask with an inorganic material on the sacrificial layer, then patterning the sacrificial layer and the layer to be structured through the mask, and, finally, removing the sacrificial layer and the mask.

Abstract: A method for producing structures having a high aspect ratio includes the following steps: a material of the structure to be produced is provided in the form of a layer, a mask is applied to the layer, the layer is subjected to dry etching using the mask, thereby forming redepositions of the layer material on side walls of the mask and the mask is removed, so that a structure having a high aspect ratio is left behind. The method enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.

Abstract: In a method for the production of a spacer layer in a structure in a first step a structure is produced by anisotropic dry etching, and in a further step an oxide layer is deposited with an organic silicon precursor at a pressure of p=0.2-1 bar and a temperature of 200.degree. C. to 400.degree. C.

Abstract: An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the trench. The components are in this case arranged in different planes on the substrate surface and on the trench bottom. The insulation structure effects vertical insulation between the components.

Abstract: Method for structuring a layer. For structuring a layer that is arranged on a lower layer of a different material using a plasma etching process, a target (14) of the material of the lower layer is arranged in an etching reactor (1). The etching process is managed such that material is sputtered from the target (14) and is deposited on surfaces of the lower layer exposed in the etching process to essentially the same degree to which the lower layer is eroded by the etching process. The method is particularly suited for structuring a polysilicon layer that is arranged on a gate oxide layer.