Patents by Inventor Manfred Engelhardt

Manfred Engelhardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7321097
    Abstract: The invention provides in a preferred embodiment an electronic component comprising a first conductive layer, a non-conductive layer and a second conductive layer. A hole is etched through the non-conductive layer. A nanotube, which is provided in said hole, links the first conductive layer to the second conductive layer in a conductive manner.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: January 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Wolfgang Hönlein, Franz Kreupl
  • Publication number: 20070218677
    Abstract: A method for forming self-aligned air-gaps as IMD wherein the interconnect lines are covered with self-aligned capping layer and wherein the process of forming the capping layer is a maskless process is provided.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 20, 2007
    Inventors: Manfred Engelhardt, Andreas Stich, Eugen Unger
  • Publication number: 20070111431
    Abstract: An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top.
    Type: Application
    Filed: September 29, 2006
    Publication date: May 17, 2007
    Inventors: Manfred Engelhardt, Andreas Stich, Guenther Schindler, Michael Schrenk
  • Patent number: 7129173
    Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 31, 2006
    Assignee: Infineon Technologies AG
    Inventors: Heike Drummer, Franz Kreupl, Annette Sänger, Manfred Engelhardt, Bernhard Sell, Peter Thieme
  • Publication number: 20060199368
    Abstract: An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.
    Type: Application
    Filed: February 22, 2006
    Publication date: September 7, 2006
    Inventors: Manfred Engelhardt, Werner Pamler, Guenther Schindler
  • Patent number: 7045070
    Abstract: The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventors: Volker Weinrich, Manfred Engelhardt, Werner Pamler, Hermann Wendt
  • Patent number: 6998338
    Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: February 14, 2006
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 6946386
    Abstract: A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: September 20, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gernot Steinlesberger, Manfred Engelhardt, Eugen Unger
  • Patent number: 6930052
    Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: August 16, 2005
    Assignee: Infineon Technologies AG
    Inventors: Siegfried Schwarzl, Manfred Engelhardt, Franz Kreupl
  • Publication number: 20050118342
    Abstract: A process for the selective and areal deposition of a catalyst is disclosed, which is intended for the growth of nanotubes, on an interconnect line in an integrated circuit or chip. The process includes providing an acidic or alkaline aqueous solution of the catalyst; applying the solution to the interconnect line; and removing the excess solution.
    Type: Application
    Filed: November 3, 2004
    Publication date: June 2, 2005
    Inventors: Manfred Engelhardt, Gernot Steinlesberger, Eugen Unger
  • Patent number: 6888244
    Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: May 3, 2005
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Guenther Schindler
  • Patent number: 6864175
    Abstract: The invention relates to a method in which an eclectically nonconductive mask layer is applied to an electrically conductive contact layer which is supported by a substrate layer. A free space is made in the mask layer. Then, a plurality of layers are electrochemically deposited in the free space. Then, layers are applied above the layer which was deposited last. Then, in a removal process, the mask layer is removed down to the height of the top layer.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: March 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Stefan Wurm
  • Publication number: 20040253806
    Abstract: A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.
    Type: Application
    Filed: May 25, 2004
    Publication date: December 16, 2004
    Applicant: Infineon Technologies AG
    Inventors: Gernot Steinlesberger, Manfred Engelhardt, Eugen Unger
  • Patent number: 6828680
    Abstract: In an integrated circuit configuration, above a first conductive structure which is embedded in a first insulating layer there are arranged a first barrier layer and a second insulating layer, in which a contact hole is provided which reaches down to the first conductive structure. Above the first barrier layer, the side walls of the contact hole are provided with spacers which act as a diffusion barrier and which reach down to the surface of the first barrier layer. A second conductive structure is arranged in the contact hole. The second conductive structure is conductively connected to the first conductive structure. During the production of the contact hole, the spacers prevent deposition of material from the first conductive structure on the surface of the second insulating layer.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: December 7, 2004
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Publication number: 20040113274
    Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.
    Type: Application
    Filed: January 7, 2004
    Publication date: June 17, 2004
    Inventors: Manfred Engelhardt, Guenther Schindler
  • Publication number: 20040094414
    Abstract: The invention relates to a biosensor that is provided with a first electrode having a first holding area and a second electrode having a second holding area for holding probe molecules which can bind macromolecular biopolymers to be detected. The first electrode and the second electrode are arranged in relation to one another in such a way that essentially unbent field lines of a generated electric field can be embodied between said electrodes.
    Type: Application
    Filed: December 9, 2002
    Publication date: May 20, 2004
    Inventors: Manfred Engelhardt, Alexander Frey, Franz Hofmann, Christl Lauterbach, Roland Thewes
  • Publication number: 20040092093
    Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.
    Type: Application
    Filed: September 3, 2003
    Publication date: May 13, 2004
    Inventors: Siegfried Schwarzl, Manfred Engelhardt, Franz Kreupl
  • Patent number: 6730562
    Abstract: A method for structuring ferroelectric layers on semiconductor substrates retains or regenerates the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components. The addition of H2O or O2 results principally in the recovery of the electrostatic breakdown strength of the ferroelectric layer, which is of importance in particular when the ferroelectric serves as a dielectric of a storage capacitor and has to withstand electric fields of 5-10×106 V/m without a significant leakage current.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 4, 2004
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Walter Hartner, Frank Hintermaier, Günther Schindler, Volker Weinrich
  • Patent number: 6716643
    Abstract: A method for fabricating a contact hole for a semiconductor memory element. The memory element includes a silicon substrate, an intermediate dielectric layer on the substrate, and an upper layer on the intermediate dielectric layer. The method includes forming a perforated mask on the upper layer, the mask including a material that exhibits temperature stability. The upper layer and a depression are etched into the intermediate dielectric layer as far as a residual thickness using the perforated mask. A layer including O3/TEOS-SiO2 is deposited onto a structure thus obtained. The layer including O3/TEOS-SiO2 is removed from a bottom of the depression by etching. The depression is lowered by etching to produce the contact hole as far as an interface with the silicon substrate, the silicon substrate being uncovered, and the layer including O3/TEOS-SiO2 serving as a lateral seal of the upper layer during the lowering of the depression.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: April 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Volker Weinrich
  • Publication number: 20040048479
    Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 11, 2004
    Inventors: Heike Drummer, Franz Kreupl, Annette Sanger, Manfred Engelhardt, Bernhard Sell, Peter Thieme