Abstract: A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

Abstract: There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

Abstract: The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A method of monitoring the temperature of a rapid thermal annealing (RTA) process and a test wafer for use in this process are disclosed. The method includes the step of forming a distorted surface region in a crystalline semiconductor wafer and the mounting of the wafer in a process chamber for performing the RTA process in a reaction gas containing ambient. The distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film. The increase of the reaction product film thickness enables an increase of the film thickness measurement accuracy and thus the accuracy in determining the RTA temperature homogeneity. In one embodiment, a distorted surface region in a crystalline silicon test wafer is produced by implanting ions at low doses into a wafer substrate up to a pre-amorphization level of the surface crystalline lattice.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract: A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

Abstract: In manufacturing a semiconductor device, an etch stop layer is formed on a cobalt silicide layer during a heat treatment when the cobalt and silicon are transformed in a low resistance phase of cobalt silicide. During a predefined time period, oxygen is added to an inert gas ambient and leads to the formation of silicon oxide on the cobalt silicide. Thus, the present invention avoids a deposition step which would otherwise be necessary for forming the silicon oxide layer on top of the cobalt suicide.

Abstract: Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.

Abstract: A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

Abstract: A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

Abstract: A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract: A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion concentration. In a subsequent single oxidation step, an oxide layer is formed having a thickness that varies in conformity with the ion concentration. This method may advantageously be applied to the formation of a gate insulation layer in a field effect transistor.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A transistor having a gate insulation layer whose peripheral portion has an increased thickness and a method of fabricating these transistor devices is disclosed. The peripheral portions with increased thickness of the gate insulation layer significantly reduce the injection of charge carriers into the gate insulation layer. Accordingly, the transistors described in the present application exhibit an improved long-time reliability. In addition, the lateral penetration of ions beneath the gate insulation layer for forming the lightly-doped drain and/or the lightly doped source is increased since the implantation may be performed at a tilt angle with respect to the perpendicular direction which is the conventionally used direction of the implantation step.

Abstract: In one illustrative embodiment, the present invention is directed to forming a masking layer (104) above a semiconducting substrate (102), forming an opening (105) in the masking layer (104), forming sidewall spacers (109) that define an exposed surface of said substrate lying between the sidewall spacers (109), and forming a layer of gate dielectric material (108) on the exposed surface of the substrate. The method further comprises forming a layer of polysilicon in the opening (105) and on the gate dielectric layer (108), removing portions of the polysilicon layer lying outside the opening (105) to define a gate electrode (111), forming a layer of refractory metal above the gate electrode (111), converting at least some of the refractory metal layer to a metal silicide region (112) above the gate electrode (111), and removing the masking layer (104).