Abstract: A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by providing a conductive layer enclosing the gate electrode so as to significantly increase the surface portion of the gate electrode having a low electric resistance. For example, providing a substantially inverted U-shaped silicide layer enclosing the gate electrode leads to a decrease in the electrical resistance of about 67% with a given aspect ratio of about 1. Moreover, reducing the gate length, i.e., increasing the aspect ratio of the gate electrode results in a nearly complete independence of the gate resistance from the gate length.

Abstract: A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides with oxide or another dielectric for protection during subsequent processing. Anisotropic etching is used to form shallow trenches in the substrate on either side of the gate conductor. The trenches are bounded by the dielectric-coated gate conductor and by dielectric isolation regions, or by an adjacent gate conductor in the case of non-isolated transistors. A selective epitaxy technique may then be used to grow a layer within each trench of a material having a bandgap lower than that of the semiconductor substrate. The lower-bandgap material is preferably grown only on the exposed semiconductor surfaces in the trenches, and not on the surrounding dielectric regions.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and forming a first dielectric spacer adjacent a first portion of the dielectric layer adjacent the gate conductor and above a second portion of the dielectric layer above the LDD region. The method also includes introducing a dopant into a source/drain region of the structure and removing a third portion of the dielectric layer above the gate conductor, the second portion of the dielectric layer above the LDD region, and the first dielectric spacer. In addition, the method includes forming a first conductive layer above the gate conductor, adjacent the first portion of the dielectric layer and above the LDD region, and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A method is described which can be used to form gate structures of very small dimensions in a semiconductor device. The method may be used to avoid employment of highly-sophisticated and cost-intensive DUV photolithography. In one illustrative embodiment, the method comprises forming a gate electrode layer, forming a first mask layer above the gate electrode layer, and forming a sidewall spacer adjacent the sidewalls of the first mask layer. Thereafter, the method comprises forming a second mask layer above a portion of the sidewall spacer and the first mask layer, removing portions of the sidewall spacer to define a hard mask comprised of a portion of the sidewall spacer, and patterning the gate electrode layer using the hard mask to define a gate electrode of the device.

Abstract: A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.

Abstract: Methods of fabricating a silicide layer on a substrate or transistor structures thereon are provided. An exemplary method includes the steps of depositing a layer of metal on a substrate that has a pn junction. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer. Any unreacted metal is removed. The substrate and the silicide layer are heated above the agglomeration threshold temperature of any filaments of the silicide layer penetrating the pn junction but below the agglomeration threshold temperature of the silicide layer. The method eliminates silicide filaments, particularly in cobalt silicide processing, that can otherwise penetrate the pn junction of a transistor source/drain region a lead to reverse-bias diode-leakage currents.

Abstract: Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.