Patents by Inventor Manfred Kotek
Manfred Kotek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9754859Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.Type: GrantFiled: September 25, 2013Date of Patent: September 5, 2017Assignee: Infineon Technologies AGInventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
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Patent number: 9698247Abstract: A semiconductor arrangement is produced by providing a semiconductor carrier of a second conduction type and epitaxially growing a first semiconductor zone of a first conduction type on the carrier. The first semiconductor zone includes a semiconductor base material doped with first and second dopants which are made of different substances which are both different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes a decrease or an increase of a lattice constant of the first semiconductor zone. The second dopant causes one or both of hardening of the first semiconductor zone and an increase of the lattice constant of the first semiconductor zone if the first dopant causes a decrease, or a decrease of the lattice constant of the first semiconductor zone if the first dopant causes an increase.Type: GrantFiled: March 16, 2016Date of Patent: July 4, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Manfred Kotek, Johannes Baumgartl, Markus Harfmann, Christian Krenn, Thomas Neidhart
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Patent number: 9406564Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.Type: GrantFiled: November 21, 2013Date of Patent: August 2, 2016Assignee: Infineon Technologies AGInventors: Manfred Engelhardt, Johannes Baumgartl, Manfred Kotek, Hans-Joachim Schulze
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Publication number: 20160197164Abstract: A semiconductor arrangement is produced by providing a semiconductor carrier of a second conduction type and epitaxially growing a first semiconductor zone of a first conduction type on the carrier. The first semiconductor zone includes a semiconductor base material doped with first and second dopants which are made of different substances which are both different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes a decrease or an increase of a lattice constant of the first semiconductor zone. The second dopant causes one or both of hardening of the first semiconductor zone and an increase of the lattice constant of the first semiconductor zone if the first dopant causes a decrease, or a decrease of the lattice constant of the first semiconductor zone if the first dopant causes an increase.Type: ApplicationFiled: March 16, 2016Publication date: July 7, 2016Inventors: Hans-Joachim Schulze, Manfred Kotek, Johannes Baumgartl, Markus Harfmann, Christian Krenn, Thomas Neidhart
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Patent number: 9306010Abstract: A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.Type: GrantFiled: March 14, 2012Date of Patent: April 5, 2016Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Manfred Kotek, Johannes Baumgartl, Markus Harfmann, Christian Krenn, Thomas Neidhart
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Publication number: 20150137144Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: Infineon Technologies AGInventors: Manfred Engelhardt, Johannes Baumgartl, Manfred Kotek, Hans-Joachim Schulze
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Publication number: 20140021637Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.Type: ApplicationFiled: September 25, 2013Publication date: January 23, 2014Applicant: Infineon Technologies AGInventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
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Patent number: 8564061Abstract: A semiconductor device has elongate plug structures extending in the lateral direction. The plug structures serve as electrical lines in order to enable locally defined lateral current flows within the cell array, within edge regions or logic regions of the semiconductor device.Type: GrantFiled: May 18, 2005Date of Patent: October 22, 2013Assignee: Infineon Technologies AGInventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
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Publication number: 20130240902Abstract: A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Hans-Joachim Schulze, Manfred Kotek, Johannes Baumgartl, Markus Harfmann, Christian Krenn, Thomas Neidhart
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Patent number: 7863104Abstract: A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips.Type: GrantFiled: October 7, 2008Date of Patent: January 4, 2011Assignee: Infineon Technologies AGInventors: Werner Kroeninger, Manfred Kotek, Adolf Koller, Abdul Rahman Mohamed
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Publication number: 20090098684Abstract: A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips.Type: ApplicationFiled: October 7, 2008Publication date: April 16, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Werner Kroeninger, Manfred Kotek, Adolf Koller, Abdul Rahman Mohamed
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Patent number: 7498194Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.Type: GrantFiled: April 11, 2007Date of Patent: March 3, 2009Assignee: Infineon Technologies AGInventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
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Publication number: 20070178624Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.Type: ApplicationFiled: April 11, 2007Publication date: August 2, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
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Patent number: 7250343Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).Type: GrantFiled: November 12, 2004Date of Patent: July 31, 2007Assignee: Infineon Technologies AGInventors: Manfred Kotek, Oliver Häberlen, Martin Pölzl, Walter Rieger
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Patent number: 7233059Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.Type: GrantFiled: May 20, 2004Date of Patent: June 19, 2007Assignee: Infineon Technologies AGInventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
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Patent number: 7186618Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.Type: GrantFiled: October 29, 2004Date of Patent: March 6, 2007Assignee: Infineon Technologies AGInventors: Martin Pölzl, Franz Hirler, Oliver Häberlen, Manfred Kotek, Walter Rieger
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Publication number: 20050269711Abstract: A semiconductor device has elongate plug structures extending in the lateral direction. The plug structures serve as electrical lines in order to enable locally defined lateral current flows within the cell array, within edge regions or logic regions of the semiconductor device.Type: ApplicationFiled: May 18, 2005Publication date: December 8, 2005Applicant: Infineon Technologies AGInventors: Walter Rieger, Franz Hirler, Martin Poelzl, Manfred Kotek
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Publication number: 20050151190Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).Type: ApplicationFiled: November 12, 2004Publication date: July 14, 2005Applicant: Infineon Technologies AGInventors: Manfred Kotek, Oliver Haberlen, Martin Polzl, Walter Rieger
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Publication number: 20050145936Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.Type: ApplicationFiled: October 29, 2004Publication date: July 7, 2005Applicant: Infineon Technologies AGInventors: Martin Polzl, Franz Hirler, Oliver Haberlen, Manfred Kotek, Walter Rieger
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Publication number: 20050012215Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.Type: ApplicationFiled: May 20, 2004Publication date: January 20, 2005Inventors: Nikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba