Abstract: In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via the input path of the memory device and evaluated.

Abstract: An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage on a supply voltage line and a control circuit which is connected to the supply source for switching on and off the supply source. The control circuit can itself be switched off and regularly switched on again, wherein the control circuit includes a control unit in order to switch the supply source on and off in such a way that the internal supply voltage on the supply voltage line differs essentially by no more than a limit value as a result of capacitive charge storage.

Abstract: Dental implant (10) for supporting a dental prosthesis on a jaw bone, is equipped with a main body (12), which comprises a securing portion (14) intended to be anchored in the bone tissue and, lying opposite it, a head portion (16). The head portion (16) protrudes radially beyond the securing portion (14) with respect to the longitudinal axis of the main body (12) to form a support face (26), in such a way that, in the state of insertion in the jaw bone, the pressure of the dental implant (10) on the jaw bone is reduced, and a sinking movement of the dental implant (10) into the jaw bone is effectively avoided, even over quite long periods of time.

Abstract: A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.

Abstract: An integrated charge pump is provided, comprising: a pump capacitor having a first terminal and a second terminal; a control unit, which operates the charge pump in an alternation between a first phase and a second phase; a first switching device in order to charge the pump capacitor with a pump voltage in the first phase; a second switching device in order to pull the potential of the first terminal to a predetermined potential in the second phase, and in order to connect the second terminal of the pump capacitor to an output node, the second switching device having a first transistor in order to connect the second terminal of the pump capacitor to the output node, a substrate terminal of the first transistor being fixedly connected to the output node; and the second switching device pulling the first terminal to the predetermined potential with a gradient, the gradient being chosen such that at no point in time is a diode breakdown voltage exceeded in the first transistor.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the generator system a state control signal that commands the generators to be in an active state or a standby state, and a self-refresh oscillator that generates a self-refresh clock signal having a period suitable to refresh memory cells of the memory device. The controller uses the self-refresh clock signal to delay transitions of the state control signal from the active state to the standby state relative to corresponding state changes of at least one external signal received by the memory device.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A memory device includes: a generator system having a number of generators that supply voltage or current to the memory device, a controller that supplies to the generator system a state control signal that commands the generators to be in an active state or a standby state, and a self-refresh oscillator that generates a self-refresh clock signal having a period suitable to refresh memory cells of the memory device. The controller uses the self-refresh clock signal to delay transitions of the state control signal from the active state to the standby state relative to corresponding state changes of at least one external signal received by the memory device.

Abstract: An integrated charge pump is provided, comprising: a pump capacitor having a first terminal and a second terminal; a control unit, which operates the charge pump in an alternation between a first phase and a second phase; a first switching device in order to charge the pump capacitor with a pump voltage in the first phase; a second switching device in order to pull the potential of the first terminal to a predetermined potential in the second phase, and in order to connect the second terminal of the pump capacitor to an output node, the second switching device having a first transistor in order to connect the second terminal of the pump capacitor to the output node, a substrate terminal of the first transistor being fixedly connected to the output node; and the second switching device pulling the first terminal to the predetermined potential with a gradient, the gradient being chosen such that at no point in time is a diode breakdown voltage exceeded in the first transistor.

Abstract: A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage on a supply voltage line and a control circuit which is connected to the supply source for switching on and off the supply source. The control circuit can itself be switched off and regularly switched on again, wherein the control circuit includes a control unit in order to switch the supply source on and off in such a way that the internal supply voltage on the supply voltage line differs essentially by no more than a limit value as a result of capacitive charge storage.

Abstract: An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor.

Abstract: A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.

Abstract: Leakage in semiconductors, such as dynamic random access memory (DRAM) devices, caused by word line/bit line shorts can be avoided by locating transistors (e.g., isolator, current limiter, equalize) inside isolated p-wells.

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract: The present invention avoids leakage in semiconductors, such as dynamic random access memory (DRAM) devices, caused by word line/bit line shorts by locating transistors (e.g., isolator, current limiter, equalize) inside isolated p-wells.

Abstract: A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.