Abstract: A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.

Abstract: A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.

Abstract: A memory configuration is divided into memory blocks and allows a flexible access to redundant memory locations by using both, redundant column lines and redundant row lines of a particular memory block to repair defects of another memory block. Thus more defects can be repaired in the other memory block than there are redundant memory locations present in the other memory block. A method of accessing redundant memory locations is also provided. The memory configuration and the method of accessing redundant memory locations can be used in all memory architectures that write or read one or more bits of information per address in a parallel manner.

Abstract: A sleeve nut includes a nut (1) and a screw like sleeve (2) screwed into that nut, thereby fixing the sleeve nut to a component (7) of e.g. an aircraft, a car or the like. Between the component (7) and the nut (1) a socle (3) is inserted having at least one upright tongue (22). This socle (3) is locked against rotation with respect to the component (7). Furthermore the nut (1) is positively locked against rotation at the socle (3) by flats (21) or edges there-between respectively with the tongue (22) of the socle (3).

Abstract: A method is provided in which several rules having an identical conditional part and different consequence parts are processed more quickly in that the fuzzification and at least parts of the inference formation are carried out only once, and in which the storage capacity of a knowledge base memory can be reduced, since all identical conditional parts need be stored only once.

Abstract: An ordering method for ranking membership function values (Wi) of linguistic input values (LWEi) in a fuzzy logic processor is presented The steps of the method are:a) within the time of one processor clock, successively reading the membership function values (Wi) into holding elements (L1 . . . L4) and, after every reading, outputs of the holding elements are through-connected onto outputs (A . . . D) of a selector (SC) as determined by a selection signal (SEL);b) comparing the signals at the outputs (A . . . D) of the selector in comparators (C1,C2,C3) and generating control signals (S1 . . . S3) for a unit (SELC) which in turn generates the new selection signal (SEL); andc) writing pointers (MAX, MAX', MAX", MIN', MIN) into position registers (P1 . . . P5) with the assistance of the control signals (S1 . . . S3) such that the pointers enable a ranked access to the membership function values (Wi) in the holding elements (L1 . . . L4).

Abstract: A voltage generator circuit includes a storage capacitor with a terminal for pickup of an output voltage. A voltage generator device which can be turned on and off has an output being connected to the terminal of the storage capacitor. A first comparator device which can be turned on and off compares the output voltage with a first threshold voltage and generates a signal for turning the voltage generator device on and off. A second comparator device compares the output voltage with a second threshold voltage and generates an output signal with which the first comparator device is turned on and off.

Abstract: A charge pump assembly includes a storage capacitor having one terminal for a first supply potential and another terminal for pickup of an output potential. The assembly has one charge pump or two charge pumps being controlled by push-pull signals. Each charge pump includes a p-channel MOS transistor having a gate terminal being controlled by a first signal and having a drain-to-source path with one terminal being connected to the other terminal of the storage capacitor. A sliding capacitor has one terminal being connected to the other terminal of the drain-to-source path of the p-channel MOS transistor and another terminal being controlled by a second signal. An n-channel MOS transistor has a gate terminal being controlled by a third signal and a drain-to-source path being connected between a second supply potential and the one terminal of the sliding capacitor.

Abstract: A regulating circuit for a substrate bias voltage generator for generating a substrate bias voltage in an integrated semiconductor circuit includes a Schmitt trigger circuit disposed between a first potential and a second potential of a semiconductor circuit. The Schmitt trigger circuit has an output side and an input for controlling a hysteresis function of the Schmitt trigger circuit. An inverter array is connected downstream of the output side of the Schmitt trigger circuit. The inverter array is connected to the first potential and to a first supply potential of the semiconductor circuit in terms of supply voltage, and the inverter array has an output. The input of the Schmitt trigger circuit for controlling the hysteresis function of the Schmitt trigger circuit is connected to the output of the inverter array.

Abstract: A conductor track configuration for very large-scale integrated circuits includes at least two lower conductor tracks extending substantially in a first direction and at least two upper conductor tracks extending substantially in the first direction above the lower conductor tracks. Each of the lower conductor tracks is subdivided into segments, defining gaps between the segments. Each respective one of the segments has one contact leading to the upper conductor track disposed above the one segment. The lower conductor tracks adjacent the segments, as seen in a second direction, have one of the gaps at least in the vicinity of one of the contacts.

Abstract: A screw is captured in an assembly of concentric sleeves, the inner one of which has a flange, and an outer workpiece is clamped between the flange and the outer sleeve. The outer workpiece has a sufficiently large, beveled bore to permit radial play of the assembly. The outer sleeve has a threaded inner flange at the other end; and the two sleeves are assembled in press fit.

Abstract: The two-part nut has a socket member and a member with an internally threaded shank and a flange which is received in a transverse groove in the socket member having a central bore traversed by the shank. The shank has a groove adjacent the flange into which reach upset portions of the socket member to hold the members together with play. The socket member has alternate bores for riveting.