Abstract: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.

Abstract: An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

Abstract: In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip (1) comprises at least one contact (2) to be soldered or is electrically conductively connected to at least one contact (14d) to be soldered that is situated outside the semiconductor chip. The semiconductor chip (1) furthermore comprises a temperature sensor device (3), which determines a measurement quantity corresponding to the temperature. A processing device (4, 5) has an analog-to-digital converter (5), which is electrically conductively connected to the temperature sensor device (3) and converts the measurement quantity into at least one storable signal that represents the temperature loading. A voltage supply device (10), which is electrically conductively connected to the temperature sensor device (3) and the processing device (4, 5), supplies these components with an operating voltage. A data memory (6) serves for storing the at least one storable signal.

Abstract: A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed. The means is, during the switching of the sense amplifier to the line, placed in a conductive state for a differently long time and/or differently strongly, depending on the respective operating mode of the semiconductor memory.

Abstract: An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.

Abstract: An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).

Abstract: A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.

Abstract: An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Abstract: An integrated memory has individually addressable normal and redundant units of memory cells. A memory unit is used to store, in a normal mode, an address for one of the normal units which needs to be replaced by one of the redundant units. A comparison unit compares an address which is present on an address bus with an address stored in the memory unit and activates one of the redundant units in the event of a match being identified. The memory also has a test circuit which can be activated by a test mode signal, can reset the memory unit to an initial state, and can store an address for one of the redundant units in the memory unit for subsequently writing an identification code to this redundant unit.

Abstract: An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.

Abstract: A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.

Abstract: The invention relates to a RAM store having a shared SA structure, in which sense amplifiers (SA) arranged in SA strips (10) between two respective adjacent cell blocks are used by a plurality of bit line pairs (21, 22; 21–24) from the adjacent cell blocks and the bit line pairs (21, 22; 21–24) have respective charge equalization circuits individually associated with them for the purpose of performing charge equalization between the bit line halves of the bit line pairs (21, 22; 21–24) in a precharge phase, where a shorting transistor (30) is provided which, when prompted by a control signal (EQLx), connects the bit line halves (BLT, BLC) of the bit line pairs (21, 22; 21–24) which are in the precharge phase to one another.

Abstract: An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened.

Abstract: A semiconductor circuit comprises a fuse and a photoelement. A conduction layer of the fuse at least partly shades a photosensor region of the photoelement from a light bundle falling onto the semiconductor circuit. An arrangement for electro-optical monitoring of fuses of a semiconductor circuit additionally comprises an illumination device for generating the light bundle and a measuring device connected to two of the terminal contacts of the semiconductor circuit. In a method for the electro-optical monitoring of fuses of a semiconductor circuit a measuring device is connected to two of the terminal contacts and the semiconductor circuit is illuminated with a light bundle.

Abstract: A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.

Abstract: An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit.

Abstract: The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a–102N) of the circuit unit (101) to be tested being activated by application of at least one test signal (103) to the word line (102a–102N), the at least one word line (102a–102N) being deactivated by removal of the test signal (103) from the word line (102a–102N), the word lines among all the word lines (102a–102N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.

Abstract: A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation.

Abstract: A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.

Abstract: A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.