Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

Abstract: Certain embodiments disclosed herein provide application-specific launch optimization. Aspects of the present disclosure include one or more cost functions for each application, where each cost function corresponds to a likelihood that a particular application should be placed into a particular pre-activation state. For each of the inactive applications, a respective one of the pre-activation states is selected based on comparing cost values obtained by evaluating the cost functions. Each of the inactive applications can be moved to or maintained in the respectively-selected pre-activation state to more efficiently provide an expedited application launch experience for a user.

Abstract: Certain embodiments disclosed herein provide application-specific launch optimization. Aspects of the present disclosure include one or more cost functions for each application, where each cost function corresponds to a likelihood that a particular application should be placed into a particular pre-activation state. For each of the inactive applications, a respective one of the pre-activation states is selected based on comparing cost values obtained by evaluating the cost functions. Each of the inactive applications can be moved to or maintained in the respectively-selected pre-activation state to more efficiently provide an expedited application launch experience for a user.

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.

Abstract: A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

Abstract: Aspects of the subject technology relate to power consuming processes of electronic devices. For example, an electronic device may create, initiate, and/or modify a power consuming process of the electronic device, based in part on user power consumption information that indicates a typical amount of power consumed by a user of the electronic device. The electronic device may recommend increases in power consumption for low power consumption users and/or decreases in power consumption for high power consumption users. A power consumption process may include a visual arrangement of graphical elements that each display periodically, occasionally, and/or continuously updated information from the application, when a full user interface of the application is not displayed.

Abstract: Aspects of the subject technology relate to power consuming processes of electronic devices. For example, an electronic device may create, initiate, and/or modify a power consuming process of the electronic device, based in part on user power consumption information that indicates a typical amount of power consumed by a user of the electronic device. The electronic device may recommend increases in power consumption for low power consumption users and/or decreases in power consumption for high power consumption users. A power consumption process may include a visual arrangement of graphical elements that each display periodically, occasionally, and/or continuously updated information from the application, when a full user interface of the application is not displayed.

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Abstract: An electronic device can include a power system including a battery and one or more processors programmed to: detect that the electronic device has been connected to a power source, predict using prior usage data of the electronic device whether battery usage between an expected time of disconnection from the power source and a next expected time of connection to the power source exceeds a threshold, and if the predicted battery usage between an expected time of disconnection from the power source and a next expected time of connection to the power source does not exceed the threshold, charge the battery to a state of charge less than the full state of charge of the battery.

Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

Abstract: Aspects of the subject technology relate to power consuming processes of electronic devices. For example, an electronic device may create, initiate, and/or modify a power consuming process of the electronic device, based in part on user power consumption information that indicates a typical amount of power consumed by a user of the electronic device. The electronic device may recommend increases in power consumption for low power consumption users and/or decreases in power consumption for high power consumption users. A power consumption process may include a visual arrangement of graphical elements that each display periodically, occasionally, and/or continuously updated information from the application, when a full user interface of the application is not displayed.

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Abstract: Systems and methods for sensitive data management are disclosed. A voice-enabled device may generate audio data representing a request from a user utterance. A remote system may perform speech-processing operations, including obtaining responsive text data from a third-party application. In examples, a sensitivity designation may be received from the third-party application, which may cause the remote system to encrypt the responsive text data, redact the text data, and/or remove the text data from the remote system after the response is provided to the voice-enabled device.

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

Abstract: Aspects of the subject technology relate to power consuming processes of electronic devices. For example, an electronic device may create, initiate, and/or modify a power consuming process of the electronic device, based in part on user power consumption information that indicates a typical amount of power consumed by a user of the electronic device. The electronic device may recommend increases in power consumption for low power consumption users and/or decreases in power consumption for high power consumption users. A power consumption process may include a visual arrangement of graphical elements that each display periodically, occasionally, and/or continuously updated information from the application, when a full user interface of the application is not displayed.

Abstract: Aspects of the subject technology relate to power consuming processes of electronic devices. For example, an electronic device may create, initiate, and/or modify a power consuming process of the electronic device, based in part on user power consumption information that indicates a typical amount of power consumed by a user of the electronic device. The electronic device may recommend increases in power consumption for low power consumption users and/or decreases in power consumption for high power consumption users. A power consumption process may include a visual arrangement of graphical elements that each display periodically, occasionally, and/or continuously updated information from the application, when a full user interface of the application is not displayed.

Abstract: The present technology provides a system, method and computer-readable medium for configuration pattern recognition and inference, directed to a device with an existing configuration, through an extensible policy framework. The policy framework uses a mixture of python template logic and CLI micro-templates as a mask to infer the intent behind an existing device configuration in a bottom-up learning inference process. Unique values for device/network identifiers and addresses as well as other resources are extracted and accounted for. The consistency of devices within the fabric is checked based on the specific policies built into the extensible framework definition. Any inconsistencies found are flagged for user correction or automatically remedied by a network controller. This dynamic configuration pattern recognition ability allows a fabric to grow without being destroyed and re-created, thus new devices with existing configurations may be added and automatically configured to grow a Brownfield fabric.

Abstract: Certain embodiments disclosed herein provide application-specific launch optimization. Aspects of the present disclosure include one or more cost functions for each application, where each cost function corresponds to a likelihood that a particular application should be placed into a particular pre-activation state. For each of the inactive applications, a respective one of the pre-activation states is selected based on comparing cost values obtained by evaluating the cost functions. Each of the inactive applications can be moved to or maintained in the respectively-selected pre-activation state to more efficiently provide an expedited application launch experience for a user.