Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Abstract: The present technology provides a system, method and computer-readable medium for configuration pattern recognition and inference, directed to a device with an existing configuration, through an extensible policy framework. The policy framework uses a mixture of python template logic and CLI micro-templates as a mask to infer the intent behind an existing device configuration in a bottom-up learning inference process. Unique values for device/network identifiers and addresses as well as other resources are extracted and accounted for. The consistency of devices within the fabric is checked based on the specific policies built into the extensible framework definition. Any inconsistencies found are flagged for user correction or automatically remedied by a network controller. This dynamic configuration pattern recognition ability allows a fabric to grow without being destroyed and re-created, thus new devices with existing configurations may be added and automatically configured to grow a Brownfield fabric.

Abstract: The disclosed technology relates to a load balancing system. A load balancing system is configured to receive health monitoring metrics, at a controller, from a plurality of leaf switches. The load balancing system is further configured to determine, based on the health monitoring metrics, that a server has failed and modify a load balancing configuration for the network fabric. The load balancing system is further configured to transmit the load balancing configuration to each leaf switch in the network fabric and update the tables in each leaf switch to reflect an available server.

Abstract: The present technology provides a system, method and computer-readable medium for configuration pattern recognition and inference, directed to a device with an existing configuration, through an extensible policy framework. The policy framework uses a mixture of python template logic and CLI micro-templates as a mask to infer the intent behind an existing device configuration in a bottom-up learning inference process. Unique values for device/network identifiers and addresses as well as other resources are extracted and accounted for. The consistency of devices within the fabric is checked based on the specific policies built into the extensible framework definition. Any inconsistencies found are flagged for user correction or automatically remedied by a network controller. This dynamic configuration pattern recognition ability allows a fabric to grow without being destroyed and re-created, thus new devices with existing configurations may be added and automatically configured to grow a Brownfield fabric.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Abstract: A switch/switching fabric is configured to load balance traffic. The switch fabric includes a plurality of switches. A packet is received at a first switch of the plurality of switches. The first switch load balances the packet to a particular entity among a plurality of entities. Each of the entities is connected to one of the plurality of switches. The first switch determines a particular switch of the plurality of switches to which the packet should be directed, the particular entity being connected to the particular switch of the plurality of switches. The particular switch receives the packet, and determines which interface of the particular switch to direct the packet to the particular entity. The plurality of entities include servers and network appliances as physical devices or virtual machines.

Abstract: The disclosed technology relates to a load balancing system. A load balancing system is configured to receive health monitoring metrics, at a controller, from a plurality of leaf switches. The load balancing system is further configured to determine, based on the health monitoring metrics, that a server has failed and modify a load balancing configuration for the network fabric. The load balancing system is further configured to transmit the load balancing configuration to each leaf switch in the network fabric and update the tables in each leaf switch to reflect an available server.

Abstract: Users are matched to items and recommended friends in a social merchandising system. During registration, a user profile is created for a user among a plurality of users in the peer-to-peer marketplace. To calculate a compatibility score, a social genome is determined for the user based on social networking characteristics associated with the user. Also, a merchandise genome is determined for the user based on item characteristics associated with the user. Results are organized into a feed for the user based on the compatibility score and time. Feeds display items of friends, or as influenced by social connections and interactions.

Abstract: The present technology provides a system, method and computer-readable medium for configuration pattern recognition and inference, directed to a device with an existing configuration, through an extensible policy framework. The policy framework uses a mixture of python template logic and CLI micro-templates as a mask to infer the intent behind an existing device configuration in a bottom-up learning inference process. Unique values for device/network identifiers and addresses as well as other resources are extracted and accounted for. The consistency of devices within the fabric is checked based on the specific policies built into the extensible framework definition. Any inconsistencies found are flagged for user correction or automatically remedied by a network controller. This dynamic configuration pattern recognition ability allows a fabric to grow without being destroyed and re-created, thus new devices with existing configurations may be added and automatically configured to grow a Brownfield fabric.

Abstract: Systems and methods for sensitive data management are disclosed. A voice-enabled device may generate audio data representing a request from a user utterance. A remote system may perform speech-processing operations, including obtaining responsive text data from a third-party application. In examples, a sensitivity designation may be received from the third-party application, which may cause the remote system to encrypt the responsive text data, redact the text data, and/or remove the text data from the remote system after the response is provided to the voice-enabled device.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: Separators and mixers for delivering controlled-quality solar-generated steam over long distances for enhanced oil recovery, and associated systems and methods. A representative method includes heating water to steam at a solar field, separating a liquid fraction from the steam, directing the steam toward a target steam user via a first, steam conduit, and directing the liquid fraction toward the target steam user in parallel with the steam via second, liquid fraction conduit. The method can further include mixing the liquid fraction and the steam before delivering the combined liquid fraction and steam to the target user.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Abstract: Separators and mixers for delivering controlled-quality solar-generated steam over long distances for enhanced oil recovery, and associated systems and methods. A representative method includes heating water to steam at a solar field, separating a liquid fraction from the steam, directing the steam toward a target steam user via a first, steam conduit, and directing the liquid fraction toward the target steam user in parallel with the steam via second, liquid fraction conduit. The method can further include mixing the liquid fraction and the steam before delivering the combined liquid fraction and steam to the target user.

Abstract: A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.

Abstract: A digital item tracking system drives e-commerce with an order state that is determined based on processing events, shipping events and payment events. When a transaction occurs in a peer-to-peer marketplace the order state is updated as events occur through the point that an order is accepted by a buyer. The order can also cause an exception in which reverse digital item tracking is needed.

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.