Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

Abstract: In the field of integrated circuit (IC) design it is common to use a plurality of design constraints files to provide the appropriate operational mode when checking the design. Designers typically use the Synopsis® design constraint (SDC) format to describe the constraints in each operational mode. Each time an operational mode is tested a corresponding SDC is used. By merging a plurality of SDCs into a single most pessimistic SDC, designers are able to ensure that the device will properly operate in all the defined operational modes. Only a single run of the merged SDC in the hypothetical mode is required thereby saving time as well as avoiding potential errors from conflicting constraints in different operational modes.

Abstract: An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).

Abstract: A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

Abstract: A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m?1 is received. A code word with length N=2m?1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

Abstract: A system and process that are a hybrid of distillation and membrane separations offers a highly efficient means of separating a fluid feed mixture into organic, solid, and aqueous components. The distillation section is followed by two membrane separation sections operated in parallel, with the distillation section separating the feed mixture into an organics-rich fraction and an organics-depleted and solids-rich fraction. One membrane section operates on the organics-rich fraction and separates it into a more organics-rich sub-fraction and a water-rich, organics-depleted sub-fraction, while the other membrane section operates on the organics-depleted, solids-rich fraction from the distillation section and separates it into a solids-rich sub-fraction and a solids-depleted, water-rich sub-fraction.

Abstract: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.

Abstract: An embodiment of the invention provides a cryptographic device that draws a substantially constant current from an accessible electrical node that supplies power to the cryptographic device. Keeping the current drawn from the accessible electrical node substantially constant reduces the probability that secure information may be taken by unwanted third parties from the cryptographic device. The cryptographic device includes an active shunt current regulator, a low-pass filter, a linear voltage regulator and an AES (advanced encryption standard) circuit.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: A system and process that are a hybrid of distillation and membrane separations offers a highly efficient means of separating a fluid feed mixture into organic, solid, and aqueous components. The distillation section is followed by two membrane separation sections operated in parallel, with the distillation section separating the feed mixture into an organics-rich fraction and an organics-depleted and solids-rich fraction. One membrane section operates on the organics-rich fraction and separates it into a more organics-rich sub-fraction and a water-rich, organics-depleted sub-fraction, while the other membrane section operates on the organics-depleted, solids-rich fraction from the distillation section and separates it into a solids-rich sub-fraction and a solids-depleted, water-rich sub-fraction.

Abstract: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: A method of determining positions of one or more error bits is disclosed. The method includes receiving a BCH codeword at input circuitry of a decoder device, establishing a threshold number of correctable bits, and determining from the received BCH codeword and a root of an encoder polynomial, a value of each of one or more syndromes. The number of the one or more syndromes is twice a maximum number of correctable bits in the received BCH codeword. When the maximum number of correctable bits in the received BCH codeword is less than the threshold number of correctable bits, the value of each coefficient in a scaled error locator polynomial is determined by performing a non-iterative, closed-form solution on the scaled error locator polynomial. The scaled error locator polynomial is an original error locator polynomial scaled by a constant scale factor. The constant scale factor is determined according to the value of each of the one or more syndromes.

Abstract: A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword.

Abstract: In the field of integrated circuit (IC) design it is common to use a plurality of design constraints files to provide the appropriate operational mode when checking the design. Designers typically use the Synopsis® design constraint (SDC) format to describe the constraints in each operational mode. Each time an operational mode is tested a corresponding SDC is used. By merging a plurality of SDCs into a single most pessimistic SDC, designers are able to ensure that the device will properly operate in all the defined operational modes. Only a single run of the merged SDC in the hypothetical mode is required thereby saving time as well as avoiding potential errors from conflicting constraints in different operational modes.