Patents by Inventor Manish Kumar Singh
Manish Kumar Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974215Abstract: As described herein, a system, method, and computer program are provided for proactive 5G leg estimation. During an initial access procedure by a user equipment on a 4G leg of a 4G-LTE network, an eNodeB of the 4G-LTE network computes a parameter for the user equipment. Further, the eNodeB of the 4G-LTE network conditionally allows an addition of a 5G leg to the 4G-LTE network for the user equipment, based on the parameter computed for the user equipment.Type: GrantFiled: November 21, 2022Date of Patent: April 30, 2024Assignee: AMDOCS DEVELOPMENT LIMITEDInventors: Sagar Tayal, Manish Kumar Singh
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Publication number: 20240006890Abstract: A device may calculate a reactive power setpoint associated with a distributed energy resource (DER) electrically coupled to a power distribution network, based on a local voltage value associated with the DER. The device may control a reactive power output of the DER in association with regulating voltage at the power distribution network, based on the reactive power setpoint.Type: ApplicationFiled: June 20, 2023Publication date: January 4, 2024Inventors: Guido CAVRARO, Manish Kumar SINGH
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Publication number: 20230377912Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to a peripheral edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Manish Kumar SINGH, Bo-Wei CHOU, Jui-Ming SHIH, Wen-Yu KU, Ping-Jung HUANG, Pi-Chun YU
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Patent number: 11784065Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to an edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.Type: GrantFiled: May 6, 2019Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Manish Kumar Singh, Bo-Wei Chou, Jui-Ming Shih, Wen-Yu Ku, Ping-Jung Huang, Pi-Chun Yu
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Publication number: 20230143595Abstract: The present invention provides the sterilization of an ophthalmic composition comprising timolol or salt thereof optionally with pharmaceutically acceptable agent(s) wherein the sterilization is achieved through aseptic filtration technique. Further the present invention provides the sterilization process by optimising the process parameters by varying the heating time at a temperature to control the viscosity of the ophthalmic composition of present invention through aseptic filtration technique wherein the filtration is done under aseptic condition through 0.45 ?m clarification pre-filter followed by 0.2? sterilizing grade filter. The process is simple and economical.Type: ApplicationFiled: March 30, 2021Publication date: May 11, 2023Inventors: Manish Kumar SINGH, Sai Kiran JANA, Mallinath HARWALKAR, Kishor DEO, Deepak BAHRI
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Patent number: 11533677Abstract: As described herein, a system, method, and computer program are provided for proactive 5G leg estimation. During an initial access procedure by a user equipment on a 4G leg of a 4G-LTE network, an eNodeB of the 4G-LTE network computes a parameter for the user equipment. Further, the eNodeB of the 4G-LTE network conditionally allows an addition of a 5G leg to the 4G-LTE network for the user equipment, based on the parameter computed for the user equipment.Type: GrantFiled: November 2, 2020Date of Patent: December 20, 2022Assignee: AMDOCS DEVELOPMENT LIMITEDInventors: Sagar Tayal, Manish Kumar Singh
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Publication number: 20220113685Abstract: Techniques for ripple-type control of networked physical systems such as power systems, water systems, and others are provided. As one example, a device includes at least one processor configured to determine, for a first controllable device in a system, based on a measurement of an output parameter and a minimum output parameter value, an output violation value for the first device. The processor is further configured to determine, based on a present input value for the first device, the output violation value, and an assistance requisition value corresponding to a second device, a target input value for the first device. The processor is further configured to cause the first controllable device to modify operation based on the target input value and a maximum input value for the first controllable device.Type: ApplicationFiled: October 14, 2021Publication date: April 14, 2022Inventors: Guido CAVRARO, Andrey BERNSTEIN, Manish Kumar SINGH
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Patent number: 11014840Abstract: Methods of and systems for removing organic substance from condensate generated from an industrial evaporation process are provided. The condensate comprises water and the organic substance. The methods and systems provide solutions related to enthalpy recovery of industrial evaporation processes such as, for example, sugar cane juice evaporation processes, dairy evaporation processes, coffee processing evaporation processes, fruit juice evaporation processes, soup evaporation processes, and chemical industry evaporation processes.Type: GrantFiled: July 27, 2018Date of Patent: May 25, 2021Assignee: Ecolab USA Inc.Inventors: Yogesh Bhole, Seong-Hoon Yoon, Manish Kumar Singh
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Patent number: 11000037Abstract: An object of the present invention is to provide a benzylamide compound or a salt thereof that controls a mite. The present invention provides a benzylamide compound represented by Formula (1): or a salt thereof, wherein R1 represents C1-6 alkyl or C1-6 haloalkyl; R2 and R3 are identical or different and each represent hydrogen, halogen, cyano, nitro, C1-6 alkyl, or the like; R4 represents hydrogen, formyl C1-6 alkyl, or the like; R5 and R6 are identical or different and each represent hydrogen, halogen, or C1-6 alkyl, or the like; R7, R8, R9, R10, and R11 are identical or different and each represent hydrogen, halogen, or the like; X represents oxygen or sulfur; and n represents an integer of 0 to 2.Type: GrantFiled: July 14, 2017Date of Patent: May 11, 2021Assignee: OAT AGRIO CO., LTD.Inventors: Tetsuya Imai, Surendra Kumar Kumawat, Manish Kumar Singh, Pramod Kumar Chauhan, Amol Vasant Shelke, Rajesh Kumar Singh, Ram Kishore, Ashish Bhatt
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Patent number: 10796759Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.Type: GrantFiled: May 16, 2019Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20190281824Abstract: An object of the present invention is to provide a benzylamide compound or a salt thereof that controls a mite. The present invention provides a benzylamide compound represented by Formula (1): or a salt thereof, wherein R1 represents C1-6 alkyl or C1-6 haloalkyl; R2 and R3 are identical or different and each represent hydrogen, halogen, cyano, nitro, C1-6 alkyl, or the like; R4 represents hydrogen, formyl C1-6 alkyl, or the like; R5 and R6 are identical or different and each represent hydrogen, halogen, or C1-6 alkyl, or the like; R7, R8, R9, R10, and R11 are identical or different and each represent hydrogen, halogen, or the like; X represents oxygen or sulfur; and n represents an integer of 0 to 2.Type: ApplicationFiled: July 14, 2017Publication date: September 19, 2019Inventors: Tetsuya Imai, Surendra Kumar Kumawat, Manish Kumar Singh, Pramod Kumar Chauhan, Amol Vasant Shelke, Rajesh Kumar Singh, Ram Kishore, Ashish Bhatt
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Publication number: 20190272873Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Publication number: 20190259636Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to an edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Manish Kumar SINGH, Bo-Wei CHOU, Jui-Ming SHIH, Wen-Yu KU, Ping-Jung HUANG, Pi-Chun YU
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Patent number: 10311952Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: GrantFiled: March 27, 2018Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 10301205Abstract: The present disclosure relates to a formulation and a process for the removal of inorganic impurities from waste water. The formulation consists of a blend of at least one alkali metal aluminate, at least one cationic organic coagulant and optionally at least one alkalinating agent in pre-determined proportions. The process for decontamination using the afore-stated formulation includes steps such as admixing, settling, microfiltration and optionally acidification, ultrafiltration and reverse osmosis. The disclosure further provides an apparatus for the removal of inorganic impurities from waste water.Type: GrantFiled: February 17, 2015Date of Patent: May 28, 2019Assignee: ECOLAB USA INC.Inventors: Tarun Kumar Bera, Manish Kumar Singh, Yogesh Bhole
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Patent number: 10283384Abstract: A method for etching an etch layer formed on a front side of a wafer and a wafer etching apparatus are provided. The wafer etching apparatus includes a first flow channel, a temperature-regulating module, and a second flow channel. The first flow channel is configured to carry a preheated/precooled liquid for controlling a temperature of a wafer. The temperature-regulating module is coupled to the first flow channel. The temperature-regulating module is configured to control a temperature of the liquid in the first flow channel. The second flow channel is configured to carry an etchant for etching an etch layer formed on a front side of the wafer. The method includes: controlling the temperature of the wafer by using the preheated/precooled liquid; and etching the etch layer with the etchant.Type: GrantFiled: April 27, 2015Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Manish Kumar Singh, Bo-Wei Chou, Jui-Ming Shih, Wen-Yu Ku, Ping-Jung Huang, Pi-Chun Yu
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Publication number: 20190031543Abstract: Methods of and systems for removing organic substance from condensate generated from an industrial evaporation process are provided. The condensate comprises water and the organic substance. The methods and systems provide solutions related to enthalpy recovery of industrial evaporation processes such as, for example, sugar cane juice evaporation processes, dairy evaporation processes, coffee processing evaporation processes, fruit juice evaporation processes, soup evaporation processes, and chemical industry evaporation processes.Type: ApplicationFiled: July 27, 2018Publication date: January 31, 2019Applicant: Ecolab USA Inc.Inventors: Yogesh Bhole, Seong-Hoon Yoon, Manish Kumar Singh
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Publication number: 20180218770Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.Type: ApplicationFiled: March 27, 2018Publication date: August 2, 2018Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
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Patent number: 9941470Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.Type: GrantFiled: January 11, 2017Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Sheng Yang, Chih-Yang Chang, Chin-Chieh Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Yu-Wen Liao, Manish Kumar Singh
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Patent number: 9934853Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.Type: GrantFiled: February 6, 2017Date of Patent: April 3, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen