Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: A method that is performed for backing up data. The method includes obtaining an asset backup request; and in response to the asset backup request: obtaining an asset and an asset entry associated with the asset backup request; dividing the asset into pseudo-assets using the asset entry; storing the pseudo-assets across backup storages to generate pseudo-asset backups; initiating the merging of the pseudo-asset backups to generate an asset backup; and updating asset backup metadata based on the asset backup.

Abstract: A wave launcher may include a printed circuit board (PCB) that includes a pin that receives a radio frequency (RF) signal. The wave launcher may include a cylinder configured to be electrically coupled to the pin and define an opening. The cylinder may receive the RF signal from the pin, form a transition from coplanar to Goubau line structure with a plate, and generate the surface wave. The wave launcher may include an insulator configured to be physically positioned within the opening and between the cylinder and a power line. The insulator may mechanically isolate the cylinder from the power line and permit the cylinder to launch the surface wave on the power line. The wave launcher may include the plate electrically coupled to a pad and may provide a reference for the pin and the cylinder. The pin and the cylinder may be physically positioned proximate the plate.

Abstract: Devices, methods, and systems for monitoring and/or assessing compliance with infectious disease guidance for reducing infectious disease transmissions are described herein. The systems may include sensing devices at or within a facility and computing devices to compare data based on outputs from the sensing devices with guidance and/or recommendations for mitigating infectious disease transmission. Various compliance parameters may be identified as being relevant to the guidelines and measurable with outputs from the sensing devices. Various compliance parameters may be identified as being relevant to the guidelines, but not measurable with outputs from the sensing devices. The compliance parameters may be individually scored or scored in groups, including the compliance parameters not measureable with outputs from the sensing devices, and a score relative to a facility or group of facilities may be provided. The scores may be presented to via a dashboard.

Abstract: A method for converting alkanes to olefins includes contacting a feed stream comprising alkanes with an oxidative dehydrogenation that does not comprise tellurium catalyst in a reaction zone and dehydrogenating the alkanes without a co-feed of oxygen to yield a product stream having olefins. The oxidative dehydrogenation catalyst has the formula: MovVwNbyAzOx, where v is 1.0, w is from 0.1 to 0.5, y is from 0.001 to 0.3, A is Bi, Sb, Pr, or mixtures thereof, z is from 0.01 to 0.3, and x charge-balances the structure. The oxidative dehydrogenation catalyst has a crystallographic structure with Pba2-32 space group, characterized by reflections determined with Cu-K? X-ray diffraction (XRD) as follows.

Abstract: Various embodiments include methods and devices for implementing a secure user interface. The method may include generating a secure user interface display in a secure execution environment, generating a non-secure display in a normal execution environment, combining the secure user interface and the non-secure display into a combined display, and presenting the combined display via a display device.

Abstract: An integrated circuit on a production die comprises a device under test (DUT) cell array formed in a fill region on the production die, the DUT cell array comprising a plurality of DUT transistor structures configured for voltage contrast (VC) detection of electrical opens on the production die. The DUT transistor structures comprise one or more vias that are not located on power lines or signal lines, such that the DUT transistor structures are not connected to each other or to the electrically functioning transistors. A guard ring buffer is formed at a transition between the active transistor region and the DUT cell array.

Abstract: The present invention provides a data processing system and method for operating an enterprise application to execute one or more tasks including a pick-pack-ship task. The invention includes generating a graphical user interface with one or more data points providing one or more item data, one or more lot data for the item data, and one or more handling unit data for the lot data to generate a pick-pack ship projection on the interface based on Artificial intelligence processing of a historical dataset.

Abstract: Various examples of improving an in-memory graph query engine using a persisted storage component are provided. The method includes updating data stored in an in-memory graph query engine and, based on updating the data, converting the data to a plain text form that may be more efficiently stored in the persistent storage component. The method further includes updates to additional in-memory graph query engines from the persistent storage component such that in-memory data stored in the graph query engines is synchronized.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

Abstract: Apparatus and methods for implementing an adaptive Dynamic Temperature Range (DTR) control mechanism to extend dynamic temperature range. A DTR control manager is provided to initiate retrain/recalibrate high-speed IO (input-output) links without link reset and extend the dynamic temperature range to the entire operating range based on thermal and other conditions. The DTR control manager ensures optimized retraining/recalibration of the link, which is based on system level parameters (like ambient temperature, fan speed, thermal zone of the devices etc.) and other environmental conditions. In some embodiments the mechanism or algorithm of the DTR control manager can be implemented in a BMC (Baseboard Management controller) or the like and hence enables the adaptive DTR solution in an operating system (OS) agnostic and seamless manner.

Abstract: Compositions comprising Group V/III nanowires, and methods of making such nanowires are described. Some compositions comprise one or more core-shell nanowires comprising a core and a first shell surrounding or substantially surrounding the core. The core is formed from GaAs(1?y)Sby, where y=about 0.03-0.07 and the first shell is formed from GaAs(1?x)SbxN, where x=0.27-0.34. The nanowires have an average emission maximum of 1.4-1.7 ?m. Some nanowires further comprise a second shell surrounding or substantially surrounding the first shell. The second shell is formed from a Group V/III material such as Ga1?mAlmAs, where m=0-0.2. Some nanowires have the structure GaAs(0.93-0.97)Sb(0.03-0.07)/GaAS(0.66-0.73)Sb(0.27-0.34)N/Ga(0.8-1)Al(0-0.2)As.

Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

Abstract: A method for performing data backup includes: receiving a backup request specifying a file where the file is stored in a shared storage. Additionally, in response to the backup request: retrieving, by a primary data node, properties of the file; determining, by the primary data node, resource availability for plurality of secondary data nodes where the primary data node and the plurality of secondary data nodes is operatively connected to the shared storage and a backup storage; logically dividing, by the primary data node, the file into a plurality of segments using at least the properties of the file; and coordinating, by the primary data node, the backup of the file using the plurality of segments and the resource availability of the plurality of secondary data nodes.

Abstract: A computing system may include a model training engine configured to train a supervised learning model with a training set comprising training probability distributions computed for training dies through a local phase of a volume diagnosis procedure. The computing system may also include a volume diagnosis adjustment engine configured to access a diagnosis report for a given circuit die that has failed scan testing and compute, through the local phase of the volume diagnosis procedure, a probability distribution for the given circuit die from the diagnosis report. The volume diagnosis adjustment engine may also adjust the probability distribution into an adjusted probability distribution using the supervised learning model and provide the adjusted probability distribution for the given circuit die as an input to a global phase of the volume diagnosis procedure to determine a global root cause distribution for multiple circuit dies that have failed the scan testing.

Abstract: Machine learning (ML) processes ranks data instances to determine when to adjust parameters of a machine learning model. Data instances are ranked by receiving data instances. Further, ranked instances are determined based on the data instances and a machine learning model. A metric is determined based on the ranked instances. An adjusted machine learning model is generated by adjusting one or more parameters of the machine learning model based on the metric.

Abstract: Embodiments of the invention relate to generating backups of applications. The user or administrator that monitors the backup is notified of those files and/or folders that have not been backed up in the most recent backup. Further, embodiments of the invention enable alerts to be initiated when a particular file or folder has not been backed up over multiple backups or over a predetermined period. As a result, the user or administrator can have a better understanding of the protection and lack of protection that the present backups are providing.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

Abstract: The present invention generally relates to system, method and graphical user interface for executing one or more tasks in dynamic data driven enterprise application. The invention includes creation of rules on a rule creation interface by one or more syntax from a rule creation syntax data library. The invention provides machine learning models driven rule engine for executing the tasks.

Abstract: B-cell maturation antigen (BCMA) is expressed on malignant plasma cells. The present invention provides methods for treating multiple myeloma using bispecific antibodies (bsAbs) that bind to both BCMA and CD3 and activate T cells via the CD3 complex in the presence of BCMA-expressing tumor cells. In certain embodiments, the bispecific antigen-binding molecules of the present invention are capable of inhibiting the growth of tumors expressing BCMA.